FTS128K32-XXX
128Kx32 SRAM MODULE
FEATURES
Packaging
Access Times of 15, 17, 20, 25, 35, 45, 55ns
MIL-STD-883
M5004
Devices Available
• 66 pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP
• 68 lead, 40mm CQFP (G4T)
1
, 3.56mm (0.140")
Low Power CMOS
TTL Compatible Inputs and Outputs
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Devices are upgradeable to 512Kx32
• 68 lead, 22.4mm CQFP (G2U), 3.56mm (0.140"),
• 68 lead, 22.4mm (0.880") square, CQFP (G2L),
5.08mm (0.200") high
Organised as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Commercial, Industrial and Military Temperature
Ranges
5 Volt Power Supply
FIGURE 1 – PIN CONFIGURATION FOR
FTS128K32N-XH1X
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
33
23
Top View
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
34
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
44
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
55
56
Pin Description
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
WE#1 CS#1
Block Diagram
WE#2 CS#2
WE#3 CS#3
WE#4 CS#4
OE#
A0-16
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O 0-7
I/O 8-15
I/O 16-23
I/O 24-31
66
2007
1/9
Rev 1
FIGURE 2 – PIN CONFIGURATION FOR
FTS128K32-XG4TX
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
#
GND
CS
3
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
Pin Description
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Block Diagram
WE#
OE#
A
0-16
CS
1
#
CS
2
#
CS
3
#
CS
4
#
128K X 8
128K X 8
128K X 8
128K X 8
8
CS
2
#
OE#
CS
4
#
NC
NC
NC
NC
NC
V
CC
A
12
A
13
A
14
A
15
A
16
A
11
NC
NC
8
8
8
I/O
0 - 7
I/O
8 - 15
I/O
16 - 23
I/O
24 - 31
FIGURE 3 – PIN CONFIGURATION FOR
FTS128K32-XG2UX
AND
FTS128K32-XG2LX
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
Pin Description
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3 2 1 68 67 66 65 64 63 62 61
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block Diagram
WE#1 CS#1
WE#2 CS#2
WE#3 CS#3
WE#4 CS#4
OE#
A0-16
128K x 8
128K x 8
128K x 8
128K x 8
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
NC
WE
2
#
WE
3
#
WE
4
#
NC
NC
NC
8
8
8
8
I/O 0-7
I/O 8-15
I/O 16-23
I/O 24-31
2007
2/9
Rev 1
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
V
CC
+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
TRUTH TABLE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
CAPACITANCE
T
A
= +25°C
Parameter
OE# capacitance
WE
1-4
# capacitance
HIP (PGA) H1
CQFP G4T
CQFP G2U/G2L
CS
1-4
# capacitance
Data# I/O capacitance
Address input capacitance
Symbol
Conditions
C
OE
V
IN
= 0V, f = 1.0 MHz
C
WE
V
IN
= 0V, f = 1.0 MHz
Max Unit
50 pF
pF
20
50
20
V
IN
= 0V, f = 1.0 MHz 20 pF
V
I/O
= 0V, f = 1.0 MHz 20 pF
V
IN
= 0V, f = 1.0 MHz 50 pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp (Mil)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.5
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
C
CS
C
I/O
C
AD
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
Min
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 8mA, V
CC
= 4.5
I
OH
= -4.0mA, V
CC
= 4.5
-15
Max
10
10
600
80
0.4
2.4
2.4
-17
Min
Max
10
10
600
80
0.4
2.4
-20
Min
Max
10
10
600
80
0.4
2.4
-25
Min
Max
10
10
600
60
0.4
Units
μA
μA
mA
mA
V
V
Parameter
Sym
Conditions
Min
-35
Max
10
10
600
60
0.4
2.4
2.4
-45
Min
Max
10
10
600
60
0.4
2.4
-55
Min
Max
10
10
600
60
0.4
Units
μA
μA
mA
mA
V
V
Input Leakage Current
I
LI
V
CC
= 5.5, V
IN
= GND to V
CC
Output Leakage Current
I
LO
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
Operating Supply Current
I
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
Standby Current
I
SB
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
Output Low Voltage
V
OL
I
OL
= 8mA, V
CC
= 4.5
Output High Voltage
V
OH
I
OH
= -4.0mA, V
CC
= 4.5
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
DATA RETENTION CHARACTERISTICS (For
FTS128K32L-XXX
Only)
-55°C
≤
T
A
≤
+125°C, -40°C
≤
T
A
≤
+85°C
Sym
V
CC
I
CCDR
T
CDR
T
R
Conditions
V
CC
= 2.0V
CS
³
V
CC
-0.2V
V
IN
³
V
CC
-0.2V
or V
IN
0.2V
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
NOTE: Parameter guaranteed, but not tested.
Min
2
-
0
TRC
Typ
-
1
-
Max
-
2
-
-
Units
V
mA
ns
ns
2007
3/9
Rev 1
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
Min
15
0
15
10
3
0
12
12
3
0
12
12
-15
Max
15
0
17
10
3
0
12
12
Min
17
-17
Max
17
0
20
12
3
0
12
12
Min
20
-20
Max
20
0
25
15
3
0
15
15
Min
25
-25
Max
25
0
35
20
3
0
20
20
Min
35
-35
Max
35
0
45
25
Min
45
-45
Max
45
Min
55
Units
-55
Max
ns
55
ns
0
ns
55
ns
30
ns
3
ns
0
ns
20
ns
20
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
Min
15
14
14
10
14
0
0
3
10
0
0
-15
Max
Min
17
14
15
10
14
0
0
3
10
0
-17
Max
Min
20
15
15
12
15
0
0
3
12
0
-20
Max
Min
25
20
20
15
20
0
0
3
15
0
-25
Max
Min
35
25
25
20
25
0
0
4
20
0
-35
Max
Min
45
30
30
25
30
0
0
4
25
0
-45
Max
Min
55
45
45
25
45
0
0
4
25
-55
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
FIGURE. 4 – AC TEST CIRCUIT
AC Test Conditions
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ½.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
2007
4/9
Rev 1
FIGURE 5 – TIMING WAVEFORM - READ CYCLE
CS#
OE#
READ CYCLE 2, (CS# = OE# = V
IL
, WE# = V
IH
)
READ CYCLE 2 (WE# = V
IH
)
FIGURE 6 – WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
FIGURE 7 – WRITE CYCLE - CS# CONTROLLED
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
2007
5/9
Rev 1
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