Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Std., A, and C speed grades
High drive outputs (-15mA I
OH
, 64mA I
OL
)
Power off disable outputs permit “live insertion”
Available in the following packages:
•
Industrial: SOIC, QSOP
•
Military: CERDIP, LCC, CERPACK
DESCRIPTION:
The FCT648T consists of a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data directly
from the data bus or from the internal storage registers. The FCT648T
utilizes the enable control (G) and direction (DIR) pins to control the
transceiver functions.
SAB and SBA control pins are provided to select either real- time or stored
data transfer. The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. A low input level selects real-time data and a high
selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (CPAB or
CPBA), regardless of the select or enable control pins.
FUNCTIONAL BLOCK DIAGRAM
G
DIR
CPBA
SBA
CPAB
SAB
B REG
ONE OF EIGH T CHANNELS
1D
C1
A1
A REG
1D
C1
B1
TO SEVEN OTHER CHANN ELS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
c
1999 Integrated Device Technology, Inc.
AUGUST 2000
DSC-5507/-
IDT54/74FCT648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
CPAB
CPBA
27
SAB
DIR
SAB
DIR
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
2
3
4
5
6
7
8
9
10
11
12
D24-1
SO24-2
SO24-8
E24-1
23
22
21
20
19
18
17
16
15
14
13
CPBA
SBA
G
B
1
B
2
B
3
A
4
B
4
B
5
B
6
B
7
B
8
A
5
A
6
9
10
11
12
13
14
15
16
17
18
21
20
19
4
3
2
1
28
26
25
24
23
L28-1
22
NC
INDEX
Vcc
CPAB
1
24
V
CC
SBA
A
1
A
2
A
3
NC
5
6
7
8
G
B
1
B
2
NC
B
3
B
4
B
5
A
7
A
8
B
8
B
7
GND
CERDIP/ SOIC/ QSOP/ CERPACK
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Rating
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max.
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
8T-link
PIN DESCRIPTION
Pin Names
A
1
- A
8
B
1
- B
8
CPAB, CPBA
SAB, SBA
DIR,
G
Description
Data Register A Inputs
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
8T-link
NOTE:
1. This parameter is measured at characterization but not tested.
2
NC
B
6
IDT54/74FCT648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE
(2)
Inputs
G
H
H
L
L
L
L
DIR
X
X
L
L
H
H
CPAB
H or L
↑
X
X
X
H or L
CPBA
H or L
↑
X
H or L
X
X
SAB
X
X
X
X
L
H
SBA
X
X
L
H
X
X
A
1
- A
8
Input
Output
Input
Data I/O
(1)
B
1
- B
8
Input
Input
Output
Operation or Function
Isolation
Store A and B Data
Real-Time
B
Data to A Bus
Stored
B
Data to A Bus
Real-Time
A
Data to B Bus
Stored
A
Data to B Bus
NOTES:
1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data
at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
2. H = HIGH
L = LOW
X = Don't Care
↑
= LOW-to-HIGH transition.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ± 10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State Output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
—
V
CC
= Max., V
IN
= GND or V
CC
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
µA
V
mV
mA
µA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min.
I
OH
= –6mA MIL
V
IN
=
V
IH
or V
IL
I
OH
= –8mA IND
I
OH
= –12mA MIL
I
OH
= –15mA IND
V
CC
= Min.
I
OL
= 48mA MIL
V
IN
=
V
IH
or V
IL
I
OL
= 64mA IND
(3)
V
CC
= Max., V
O
= GND
V
CC
= 0V, V
IN
or V
O
≤
4.5V
Min.
2.4
2
—
–60
—
Typ.
(2)
3.3
3
0.3
–120
—
Max.
—
—
0.55
–225
±1
V
mA
µA
Unit
V
V
OL
I
OS
I
OFF
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
3
IDT54/74FCT648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
A
BUS
B
DIR
L
G
L
CPAB
X
CPBA
X
SAB
X
SBA
L
DIR
H
G
L
CPAB
X
CPBA
X
SAB
L
SBA
X
REAL-TIME TRANSFER
BUS B TO A
REAL-TIME TRANSFER
BUS A TO B
BUS
A
BUS
B
BUS
A
BUS
B
DIR
H
L
X
G
L
L
H
CPAB
↑
CPBA
X
↑
↑
SAB
X
X
X
SBA
X
X
X
X
↑
DIR
L
H
G
L
L
CPAB
X
H or
CPBA
H or
X
SAB
X
H
SBA
H
X
STORAGE FROM
A AND/OR B
TRANSFER STORES
(1)
DATA TO A AND/OR B
NOTE:
1. Cannot transfer data to A bus and B bus simultaneously.
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