PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
, L
OW
P
HASE
N
OISE
,
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
FOUT0 and FOUT1 differential 3.3V LVPECL outputs
•
Selectable CLK, nCLK and LVCMOS reference inputs
•
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVHSTL, LVDS, SSTL
•
Maximum output frequency: 31.25MHz to 700MHz
•
Differential input or reference input frequency:
14MHz to 25MHz
•
VCO range: 250MHz - 700MHz
•
Accepts any single-ended input signal to LVCMOS with
resistor bias on nCLK input
•
Parallel interface for programming counter and output
dividers
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8432-101 is a general purpose, dual out-
put high frequency synthesizer and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance
Clocks Solutions from ICS. The VCO operates at
a frequency range of 250MHz to 700MHz. The
VCO frequency is programmed in steps equal to the value of
the input differential or single ended reference frequency. The
VCO and output frequency can be programmed using the serial
or parallel interfaces to the configuration logic. The low phase
noise characteristics of the ICS8432-101 makes it an ideal clock
source for Gigabit Ethernet, Fiber Channel 1 and 2, Infiniband
and Sonet OC3 and OC12 applications.
,&6
B
LOCK
D
IAGRAM
VCO_SEL
CLK_SEL
TEST_CLK
CLK
nCLK
0
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
nCLK
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
1
M5
M6
M7
M8
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
VCC
FOUT1
nFOUT1
VCCO
FOUT0
nFOUT0
VEE
24
23
22
CLK
TEST_CLK
CLK_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
÷
M
VCO
0
÷
N
1
N0
N1
nc
FOUT0
nFOUT0
FOUT1
nFOUT1
VEE
ICS8432-101
21
20
19
18
17
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm Package Body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432AY-101
www.icst.com/products/hiperclocks.html
1
REV. B JULY 30, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
, L
OW
P
HASE
N
OISE
,
LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values
for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-101 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
A differential clock input is used as the input to the ICS8432-101. This input is fed into the phase detector. A
25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of
250MHz to 700MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter divider force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock.
The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides
a 50% output duty cycle.
The programmable features of the ICS8432-101 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the ripple
counter. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple counter remains loaded until
the next LOW transition on nP_LOAD or until a serial event occurs. As a result the M and N bits can be hardwired to set the
ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW when operat-
ing in the parallel input mode. The relationship between the VCO frequency, the input frequency and the loop divider is defined
as follows:
fVCO = fIN x M
The M count and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock are defined as 10
≤
M
≤
28. The frequency out is defined as follows:
fOUT = fVCO = fIN x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the
S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter when
S_LOAD transitions from LOW-to-HIGH. The ripple counter divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter on each rising edge of
S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and
T1 determine the state of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data
Output of M divider
CMOS Fout
S_DATA
S_CLOCK
S_LOAD
T1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
M0:M8, N0:N2
nP_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE: The NULL timing slot must be observed.
8432AY-101
www.icst.com/products/hiperclocks.html
2
REV. B JULY 30, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
, L
OW
P
HASE
N
OISE
,
LVPECL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Unused
Power
Output
Power
Output
Power
Output
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider value as defined in Table 3C Function
table. LVCMOS / LVTTL interface levels.
No connect.
Negative supply pin. Connect to ground.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
Positive supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
Output supply pin. Connect to 3.3V.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
Forces outputs LOW, but does not effect loaded M, N, and T
values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLK.
Shift register serial input.
Data sampled on the rising edge of S_CLK.
Controls transition of data from shift register into the ripple counter.
LVCMOS / LVTTL interface levels.
Analog supply pin. Connect to 3.3V.
Clock select input. Selects between differential clock input or test
input as the PLL reference source. When HIGH, selects CLK,
nCLK inputs. When LOW, selects TEST_CLK input.
LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels.
Non-inver ting differential clock input.
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3, 4
28, 29
30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
14, 15
17
18
19
20
21
22
23
24
25
26
27
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
V
EE
TEST
V
CC
FOUT1, nFOUT1
V
CCO
FOUT0, nFOUT0
MR
S_CLOCK
S_DATA
S_LOAD
V
CCA
CLK_SEL
TEST_CLK
CLK
nCLK
nP_LOAD
VCO_SEL
Inver ting differential clock input.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into ripple counter, and when data present at N1:N0 sets
the output divide value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characterisitics, for typical values.
8432AY-101
www.icst.com/products/hiperclocks.html
3
REV. B JULY 30, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
, L
OW
P
HASE
N
OISE
,
LVPECL F
REQUENCY
S
YNTHESIZER
Test Conditions
TEST_CLK,
CLK, nCLK
M0:M8, S_LOAD,
N0:N1, S_DATA,
VCO_SEL, MR
CLK_SEL,
nP_LOAD,
S_CLOCK
51
51
Minimum Typical
Maximum
4
Units
pF
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
RPULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
KΩ
KΩ
T
ABLE
3A. P
ARALLEL
MR
H
L
nP_LOAD
X
L
↑
AND
S
ERIAL
M
ODES
F
UNCTION
T
ABLE
Inputs
N
X
Data
S_LOAD
X
X
S_CLOCK
X
X
S_DATA
X
X
Conditions
Reset. M and N counters reset.
Data on M and N inputs passed directly to ripple
counter and output divider.
TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial
event occurs.
Serial input mode. Shift register is loaded with
data on S_DATA on each rising edge of
S_CLOCK.
Contents of the shift register are passed to the
ripple counter and output divider.
Ripple counter and output divide values are
latched.
Parallel or serial input do not affect shift registers.
M
X
Data
L
Data
Data
L
X
↑
L
L
X
X
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
X
L
↑
↓
L
Data
Data
Data
X
8432AY-101
www.icst.com/products/hiperclocks.html
4
REV. B JULY 30, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
, L
OW
P
HASE
N
OISE
,
LVPECL F
REQUENCY
S
YNTHESIZER
256
M8
0
0
0
0
•
•
0
0
128
M7
0
0
0
0
•
•
0
0
64
M6
0
0
0
0
•
•
0
0
32
M5
0
0
0
0
•
•
0
0
16
M4
0
0
0
0
•
•
1
1
8
M3
1
1
1
1
•
•
1
1
4
M2
0
0
1
1
•
•
0
0
2
M1
1
1
0
0
•
•
1
1
1
M0
0
1
0
1
•
•
0
1
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
275
300
325
•
•
650
675
M Count
10
11
12
13
•
•
26
27
700
28
0
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequency correspond to differential input or test clock input frequency
of 25MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider
Value
1
2
4
8
Output Frequency
(MHz)
Minimum
Maximum
250
125
62.5
31.25
700
350
175
87.5
8432AY-101
www.icst.com/products/hiperclocks.html
5
REV. B JULY 30, 2001
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