71V2577S80BG8 datasheet, PDF - EEWORLD Datasheet

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71V2577S80BG8: DescriptionPBGA-119, Reel; Categorystorage storage; File Size295KB，22 Pages; ManufacturerIDT (Integrated Device Technology)

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71V2577S80BG8 Overview

PBGA-119, Reel

71V2577S80BG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	PBGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Manufacturer packaging code	BG119
Reach Compliance Code	not_compliant
Maximum access time	8 ns
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
memory density	4718592 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.03 A
Minimum standby current	3.14 V
Maximum slew rate	0.2 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

71V2577S80BG8 Preview

128K x 36, 256K x 18

3.3V Synchronous SRAMs

2.5V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Features

IDT71V2577S

IDT71V2579S

IDT71V2577SA

IDT71V2579SA

Description

The IDT71V2577/79 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data,

address and control registers. There are no registers in the data output

path (flow-through architecture). Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V2577/79 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will flow-through from the

array after a clock-to-data access time delay from the rising clock edge of

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequent three cycles of output data will be available to the user on the

next three rising clock edges. The order of these three addresses are

defined by the internal burst counter and the

LBO

input pin.

The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

4877 tbl 01

128K x 36, 256K x 18 memory configurations

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

Commercial and Industrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

NOTE:

and

are not applicable for the IDT71V2579.

JUNE 2003

DSC-4877/08

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Definition

(1)

Symbol

-A

ADSC

ADSP

ADV

Pin Function

Address Inputs

Address Status

(Cache Controller)

Address Status

(Processor)

Burst Address

Advance

Byte Write Enable

I/O

Active

N/A

LOW

Description

Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of

CLK and

ADSC

Low or

ADSP

Low and

Low.

Synchronous Address Status from Cache Controller.

ADSC

is an active LOW input that is used to load the

address registers with new addresses.

Synchronous Address Status from Processor.

ADSP

is an active LOW input that is used to load the

address registers with new addresses.

ADSP

is gated by

CE.

Synchronous Address Advance.

ADV

is an active LOW input that is used to advance the internal burst

counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst

counter is not incremented; that is, there is no address advance.

Synchronous byte write enable gates the byte write inputs

-BW

. If

BWE

is LOW at the rising edge of

CLK then

BWx

inputs are passed to the next stage in the circuit. If

BWE

is HIGH then the byte write inputs

are blocked and only

can initiate a write cycle.

Synchro nous byte write enables.

controls I/O

0-7

, I/O

controls I/O

8-15

, I/O

, etc. Any active

byte write causes all outputs to be disabled.

Synchronous chip enable.

is used with CS

and

to enable the IDT71V2577/79.

also gates

ADSP.

This is the clock input. All timing references for the device are made with respect to this input.

Synchronous active HIGH chip select. CS

is used with

and

to enable the chip.

Synchronous active LOW chip select.

is used with

and CS

to enable the chip.

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising

edge of CLK.

supersedes individual byte write enables.

Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge

of CLK. The data output path is flow-through (no output register).

Asynchronous burst ord er selection input. When

LBO

is HIGH, the inter-leaved burst sequence is

selected. When

LBO

is LOW the Linear burst sequence is selected.

LBO

is a static input and must not

change state while the device is operating.

Asynchrono us output enable. When

is LOW the data output drivers are enabled on the I/O pins if the

chip is also selected. When

is HIGH the I/O pins are in a high-impedance state.

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an

internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the

TAP controller.

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset

occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used

TRST

can be left floating. This pin has an internal pullup. Only available in BGA package.

Asynchronous sleep mode input. ZZ HIGH will gate the CLK inte rnally and power down the IDT71V2577/79

to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal

pull down.

3.3V core power supply.

2.5V I/O Supply.

Ground.

NC pins are not electrically connected to the device.

4877 tbl 02

BWE

LOW

-BW

CLK

I/O

-I/O

I/O

-I/O

LBO

Individual Byte

Write Enables

Chip Enable

Clock

Chip Select 0

Chip Select 1

Global Write

Enable

Data Input/Output

Linear Burst Order

I/O

LOW

N/A

HIGH

LOW

N/A

LOW

TMS

TDI

TCK

TDO

Output Enable

Test ModeSelect

Test Data Input

Test Clock

Test DataOutput

JTAG Reset

(Optional)

LOW

N/A

TRST

LOW

DDQ

Sleep Mode

Power Supply

Ground

No Connect

N/A

HIGH

N/A

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Functional Block Diagram

LBO

ADV

CEN

Burst

Sequence

INTERNAL

ADDRESS

CLK

ADSC

ADSP

CLK EN

ADDRESS

Byte 1

Write Register

Binary

Counter

CLR

Burst

Logic

17/18

A0*

A1*

128K x 36/

256K x 18-

BIT

MEMORY

ARRAY

17/18

2 -

36/18

0 -

16/17

BWE

Byte 1

Write Driver

Byte 2

Write Register

Byte 2

Write Driver

Byte 3

Write Register

Byte 3

Write Driver

Byte 4

Write Register

Byte 4

Write Driver

Enable

DATA INPUT

CLK EN

Powerdown

I/O

- I/O

I/O

- I/O

36/18

OUTPUT

BUFFER

4877 drw 01

TMS

TDI

TCK

TRST

(Optional)

JTAG

(SA Version)

TDO

6.42

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Symbol

TERM

(2)

Rating

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Terminal Voltage with

Respect to GND

Commercial

Operating Temperature

Industrial

Operating Temperature

Commerical &

Industrial Values

-0.5 to +4.6

-0.5 to V

+0.5

-0.5 to V

DDQ

+0.5

-0 to +70

-40 to +85

-55 to +125

2.0

Unit

Recommended Operating

Temperature and Supply Voltage

Grade

Commercial

Industrial

Temperature

(1)

0°C to +70°C

-40°C to +85°C

3.3V±5%

DDQ

2.5V±5%

4877 tbl 04

TERM

(3,6)

TERM

(4,6)

TERM

(5,6)

NOTES:

1. TA is the “instant on” case temperature.

Recommended DC Operating

Conditions

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

Min.

3.135

2.375

1.7

-0.3

(2)

Typ.

3.3

2.5

____

(7)

Max.

3.465

2.625

+ 0.3

DDQ

+ 0.3

(1)

0.7

Unit

4877 tbl 05

DDQ

BIAS

STG

OUT

Temperature

Under Bias

Storage

Temperature

Power Dissipation

DC Output Current

4877 tbl 03

NOTES:

1. V

(max) = V

DDQ

+ 1.0V for pulse width less than t

CYC/2

, once per cycle.

2. V

(min) = -1.0V for pulse width less than t

CYC/2

, once per cycle.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V

terminals only.

3. V

DDQ

terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed V

DDQ

during power supply ramp up.

7. TA is the “instant on” case temperature.

100 Pin TQFP Capacitance

= +25°C, f = 1.0MHz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

4877 tbl 07

119 BGA Capacitance

= +25°C, f = 1.0MHz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

4877 tbl 07a

165 fBGA Capacitance

= +25°C, f = 1.0MHz)

Symbol

I/O

Parameter

(1)

Input Capacitance

I/O Capacitance

Conditions

= 3dV

OUT

= 3dV

Max.

Unit

4877 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36

CLK

BWE

ADSC

ADSP

ADV

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/O

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

I/O

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

I/O

DDQ

I/O

DDQ

I/O

(2)

I/O

DDQ

I/O

DDQ

I/O

4877 drw 02a

NOTES:

1. Pin 14 does not have to be directly connected to V

as long as the input voltage is < V

2. Pin 64 can be left unconnected and the device will always remain in active mode.

LBO

100 TQFP

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6.42

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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