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7015S15PFG8

Description
Dual-Port SRAM, 8KX9, 15ns, CMOS, PQFP80, TQFP-80
Categorystorage    storage   
File Size186KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

7015S15PFG8 Overview

Dual-Port SRAM, 8KX9, 15ns, CMOS, PQFP80, TQFP-80

7015S15PFG8 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLQFP,
Contacts80
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time15 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
JESD-30 codeS-PQFP-G80
JESD-609 codee3
length14 mm
memory density73728 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Humidity sensitivity level3
Number of functions1
Number of terminals80
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX9
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
Features:
IDT7015S/L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 12/15/17/20/25/35ns (max.)
– Industrial: 20ns (max.)
– Military: 20/25/35ns (max.)
Low-power operation
– IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7015 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-
pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
12L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
8R
BUSY
R
Address
Decoder
13
(1,2)
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
M/S
2954 drw 01
SEM
R
(2)
INT
R
JANUARY 2002
1
©2002 Integrated Device Technology, Inc.
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