Integrated
Circuit
Systems, Inc.
ICS853P022
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
3.3V LVPECL T
RANSLATOR
F
EATURES
•
2 differential 3.3V LVPECL outputs
•
LVCMOS/LVTTL clock inputs
•
Maximum output frequency: 1.1GHz
•
Part-to-part skew: 650ps (maximum)
•
Propagation Delay: 320ps (typical)
•
Additive phase jitter, RMS: 0.03ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 3.0V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -3.0V
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS853P022 is a Dual LVCMOS / LVTTL-to-
Differential 3.3V LVPECL translator and a mem-
HiPerClockS™
ber of the HiPerClocks™ family of High Perfor-
mance Clocks Solutions from ICS. The
ICS853P022 has single ended clock inputs. The
single ended clock input accepts LVCMOS or LVTTL input
levels and translate them to LVPECL levels. The small outline
8-pin TSSOP package makes this device ideal for applica-
tions where space, high performance and low power are im-
portant.
ICS
B
LOCK
D
IAGRAM
D0
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
CC
D0
D1
V
EE
D1
ICS853P022
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
853P022AG
www.icst.com/products/hiperclocks.html
1
REV. A FEBRUARY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS853P022
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
3.3V LVPECL T
RANSLATOR
Type
Output
Output
Power
Input
Input
Power
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
LVCMOS / LVTTL clock input.
LVCMOS / LVTTL clock input.
Positive supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
D1
D0
V
CC
853P022AG
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS853P022
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
3.3V LVPECL T
RANSLATOR
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, V
CC
= 0)
to the device. These ratings are stress specifi-
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
50mA
100mA
-65°C to 150°C
101.7°C/W (0 m/s) TSSOP
112.7°C/W (0 lfpm) SOIC
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
2A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.0V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.8
35
Units
V
mA
T
ABLE
2B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.0V
TO
3.8V; V
EE
= 0V
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
Test Conditions
Minimum
0.7 * V
CC
0.3 * V
CC
10 0
-0.6
Typical
Maximum
Units
V
V
µA
mA
T
ABLE
2C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
Parameter
Output High Voltage; NOTE 1
Min
2.175
-40°C
Typ
2.275
Max
2.38
Min
2.225
1.425
25°C
Typ
2.295
1.52
Max
2.37
1.615
Min
2.295
1.44
85°C
Typ
2.33
1.535
Max
2.365
1.63
Units
V
V
1.405
1.545
1.68
V
OL
Output Low Voltage; NOTE 1
Output parameters var y 1:1 with V
CC
. V
CC
can var y +3.8V to 3.0V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
853P022AG
www.icst.com/products/hiperclocks.html
3
REV. A FEBRUARY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS853P022
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
3.3V LVPECL T
RANSLATOR
-40°C
Min
-1.125
-1.895
T
ABLE
2D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-3.0V
Symbol
V
OH
V
OL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
25°C
Max
-0.92
-1.62
85°C
Max
-0.93
-1.685
Typ
-1.025
-1.755
Min
-1.075
-1.875
Typ
-1.005
-1.78
Min
-1.005
-1.86
Typ
-0.97
-1.765
Max
-0.935
-1.67
Units
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
3. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-3.0V
OR
V
CC
= 3.0V
TO
3.8V; V
EE
= 0V
Symbol
f
MAX
t p
LH
t p
HL
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
20% to 80%
85
125
125
320
320
12
-40°C
Min
Typ
Max
1.1
600
600
55
330
0.03
200
315
100
0.03
200
285
85
180
180
320
320
12
Min
25°C
Typ
Max
1.1
475
475
50
225
0.03
200
315
190
190
300
300
12
Min
85°C
Typ
Max
1.1
410
410
50
225
Units
GHz
ps
ps
ps
ps
ps
ps
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
All parameters are measured
≤
650MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853P022AG
www.icst.com/products/hiperclocks.html
4
REV. A FEBRUARY 23, 2005
Integrated
Circuit
Systems, Inc.
ICS853P022
D
UAL
LVCMOS / LVTTL-
TO
-D
IFFERENTIAL
3.3V LVPECL T
RANSLATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
nQx
V
CC
Qx
SCOPE
Qx
nQy
LVPECL
V
EE
nQx
Qy
t
sk(o)
-1.8V to -1.0V
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
nQx
PART 1
Qx
nQy
PART 2
Qy
D0, D1
nQ0, nQ1
t
sk(pp)
Q0, Q1
tp
LH
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
O
UTPUT
R
ISE
/F
ALL
T
IME
853P022AG
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 23, 2005
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