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PMN34LN

Description
Small Signal Field-Effect Transistor
CategoryDiscrete semiconductor    The transistor   
File Size336KB,13 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric View All

PMN34LN Overview

Small Signal Field-Effect Transistor

PMN34LN Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionSC-74, TSOP-6
Reach Compliance Codecompliant
Samacsys DescriptionFET
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage20 V
Maximum drain current (ID)5.7 A
Maximum drain-source on-resistance0.034 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G6
JESD-609 codee3
Humidity sensitivity level1
Number of components1
Number of terminals6
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Polarity/channel typeN-CHANNEL
surface mountYES
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperature30
transistor applicationsSWITCHING
Transistor component materialsSILICON

PMN34LN Preview

Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
PMN34LN
µTrenchMOS™
logic level FET
M3D302
Rev. 01 — 21 March 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PMN34LN in SOT457 (TSOP6).
1.2 Features
s
Low on-state resistance in small surface mount package.
1.3 Applications
s
DC-to-DC primary side.
1.4 Quick reference data
s
V
DS
20 V
s
P
tot
1.75 W
s
I
D
5.7 A
s
R
DSon
34 mΩ
2. Pinning information
Table 1:
Pin
1,2,5,6
3
4
Pinning - SOT457 (TSOP6), simplified outline and symbol
Description
drain (d)
gate (g)
source (s)
g
s
6
5
4
d
Simplified outline
Symbol
1
Top view
2
3
MBK092
MBB076
SOT457 (TSOP6)
Philips Semiconductors
PMN34LN
µTrenchMOS™
logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
peak source (diode forward) current T
sp
= 25
°C;
pulsed; t
p
10
µs
T
sp
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 10 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
150
°C
25
°C ≤
T
j
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
20
20
±15
5.7
3.6
22.9
1.75
+150
+150
1.45
5.95
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
9397 750 10938
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 21 March 2003
2 of 12
Philips Semiconductors
PMN34LN
µTrenchMOS™
logic level FET
120
Pder
(%)
80
03aa17
120
Ider
(%)
80
03aa25
40
40
0
0
50
100
150
Tsp (°C)
200
0
0
50
100
150
200
Tsp (
°
C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
ID
(A)
10
100
µ
s
1 ms
1
DC
100 ms
10-1
10 ms
03al58
Limit RDSon = VDS / ID
tp = 10
µ
s
10-2
10-1
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse; V
GS
= 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10938
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 21 March 2003
3 of 12
Philips Semiconductors
PMN34LN
µTrenchMOS™
logic level FET
4. Thermal characteristics
Table 3:
R
th(j-sp)
Thermal characteristics
Conditions
Min Typ Max Unit
-
-
70
K/W
thermal resistance from junction to solder point
Figure 4
Symbol Parameter
4.1 Transient thermal impedance
102
Zth(j-sp)
K/W
03al57
δ
= 0.5
0.2
10
0.1
0.05
0.02
1
P
δ
=
tp
T
single pulse
tp
T
t
10-1
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 10938
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 01 — 21 March 2003
4 of 12
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