M381L6423BT1
184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx72(32Mx72*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
72-bit ECC/Parity
Revision 1.1
May. 2002
Rev. 1.1 May. 2002
M381L6423BT1
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Revision 0.1 (Aug. 1999)
1. Modified binning policy
From
To
-Z (133Mhz)
-Z (133Mhz/266Mbps@CL=2)
-8 (125Mhz)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz)
-0 (100Mhz/200Mbps@CL=2)
2.Modified the following AC spec values
From.
-Z
tAC
tDQSCK
tDQSQ
tDS/tDH
tCDLR
*1
tPRE
*1
tRPST
*1
tHZQ
*1
*1
To.
-0
+/- 1ns
+/- 1ns
+/- 0.75ns
0.75 ns
-Z
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-Y
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-0
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
: Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
Revision 0.2 (Sept. 1999)
1. Changed the odering information.
1-1. Exclude KM mark.
From
KMM381...
1-2. PCB Revison
From
- Blank: 1st generation
-A
: 2nd generation
-B
: 2nd generation
Example:KMM381L6423AT
1-3. Modified binning policy
From
- 0 (100Mhz/200Mbps@CL=2)
- Z (133Mhz/266Mbps@CL=2)
- Y (133Mhz/266Mbps@CL=2.5)
To
M381.....
To
- 0: 1st gernation
- 1: 2nd generation
- 2: 3nd generation
M381L6423AT0
To
- A0 (100Mhz/200Mbps@CL=2)
- A2 (133Mhz/266Mbps@CL=2)
- B0 (133Mhz/266Mbps@CL=2.5)
Rev. 1.1 May. 2002
M381L6423BT1
Revision 0.3 (December. 1999)
184pin Unbuffered DDR SDRAM MODULE
1. Changed from 3.3V to 2.5V in VDDSPD power.
Revision 0.4 (April. 2000)
< Page 3 >
1. Changed from 1450mil to 1250mil in PCB height.
2. Changed pin 90 from WP to NC in pin configuration table.
3. Changed in pin configuration table as followings.
pin 16 : CK0 -> CK1
pin 17 : CK0 -> /CK1
pin 137 : CK1 -> CK0
pin 138 : CK1 -> /CK0
4. Removed WP in pin description.
< Page 4>
5. Changed bypassing to reflect common Vdd/Vddq plane.
6. Added A13, BA1.
7. Removed WP from serial PD.
< Page 5>
8.
Changed Power & DC operating condition.
Parameter
I/O Reference voltage
Input logic high voltage
Input logic low voltage
Input leakage current
Output High Current (V
OUT
= 1.95V)
Output Low Current (V
OUT
= 0.35V)
< Page 6 >
Symbol
V
REF
V
IH
(DC)
V
IL
(DC)
I
I
I
O H
I
OL
From
Min
1.15
V
REF
+0.18
-0.3
-5
-15.2
15.2
To
Max
1.35
V
DDQ
+0.3
V
REF
-0.18
5
Min
0.49*VDDQ
V
REF
+0.15
-0.3
-2
-16.8
16.8
Max
0.51*VDDQ
V
DDQ
+0.3
V
REF
-0.15
2
9. Added Overshoot/Undershoot spec
. Vih(max) = 4.2V, the overshoot voltage duration is
≤
3ns at VDD.
. Vil(min) =- 1.5V, the overshoot voltage duration is
≤
3ns at VSS.
< Page 6,7 >
10. Changed AC operating conditions as follows.
From
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
0.7
Min
VREF + 0.35
VREF - 0.35
VDDQ+0.6
0.62
Max
Min
VREF + 0.31
VREF - 0.31
VDDQ+0.6
To
Max
Rev. 1.1 May. 2002
M381L6423BT1
< Page 7 >
184pin Unbuffered DDR SDRAM MODULE
11. Changed Input/Output capacitance as follows.
Parameter
Input capacitance(A
0
~ A
12
, BA
0
~ BA
1
,RAS,CAS, WE )
Input capacitance(CKE
0,
CKE
1
)
Input capacitance( CS
0
,CS
1
)
Input capacitance( CLK
0
, CLK
1,
CLK
2
)
Input capacitance(DM
0
~DM
8
)
Data & DQS input/output capacitance(DQ
0
~DQ
63
)
Data input/output capacitance(CB
0
~CB
7
)
< page 8, 9>
12. Changed AC parameters as follows.
Parameter
tDQSQ
tDV
from
+/- 0.5(PC266), +/- 0.6(PC200)
+/- 0.35tCK
to
+0.5(PC266), +0.6(PC200)
-
Removed
Comments
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
OUT1
C
OUT2
From
Min
-
-
-
-
-
-
-
Max
98
67
60
38
16
16
16
Min
69
44
44
27
6
6
6
To
Max
87
53
53
34
8
8
8
13. Added AC parameters as follows
Parameter
Output DQS valid window
Symbol
tQH
-A2(PC266@CL=2)
Min
tHPmin
-0.75ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
-B0(PC266@CL=2.5)
Min
tHPmin
-0.75ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
-A0(PC200@CL=2)
Min
tHPmin
-1.0ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
Clock half period
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
Write burst end to QFC delay on write
interrupted by Precharge
tHP
tQCS
tDQCH
tQCSW
tQCHW
tQCHWI
-
-
-
1.1
0.6
4.0
1.1
0.6
4.0
1.1
0.6
4.0
1.25ns
1.25ns
0.5tCK
1.5tCK
1.25ns
1.25ns
0.5tCK
1.5tCK
1.25ns
1.25ns
0.5tCK
1.5tCK
< Page 12>
14. Changed from 1450mil to 1250mil in Package dimension.
Revision 0.5 (April. 2000)
1. Changed from A-die to B-die.
Revision 0.6 (June. 2000)
1. Changed PCB version from T0 to T1.
Rev. 1.1 May. 2002
M381L6423BT1
Revision 0.7 (October. 2000)
1.Added DC target spec values.
2.Deleted tDAL in AC parameter X.
184pin Unbuffered DDR SDRAM MODULE
Revision 0.8 (November. 2000)
1.Changed component placement on module PCB in package dimesions.
Revision 0.9 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Revision 1.0 (Dec. 2001)
- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 47.
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 1.0W to 1.5W.
- Revised AC parameter table
From
DDR266A
Min.
tHZ
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR266B
Min.
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR200
Min.
tACmin
-400ps
tACmin
-400ps
0.25
10ns
Max.
tACmax
-400ps
tACmax
-400ps
DDR266A
Min.
-0.75
Max.
+0.75
To
DDR266B
Min.
-0.75
Max.
+0.75
DDR200
Min.
-0.8
Max.
+0.8
tLZ
tWPST
(tCK)
tPDEX
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
0.4
7.5ns
0.6
0.4
7.5ns
0.6
0.4
10ns
0.6
-
Deleted typical current in IDD spec. table
-
Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification
-
Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification
-
Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266
-
Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266
-
Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266
-
Rename tREF(Refresh interval time) to tREFI at DDR200/266
- Changed tWR value from 2tCK to 15ns.
--Rename tCDLR(Write data out to Read command) t0 tWTR
- Added tDAL(tWR+tRP)
Revision 1.1 (May. 2002)
1. Change pin locatrion of A13 from pin 103 to pin 167
Rev. 1.1 May. 2002