FM25640C-G datasheet, PDF - EEWORLD Datasheet

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FM25640C-G: DescriptionNon-Volatile SRAM, 8KX8, CMOS, PDSO8; Categorystorage storage; File Size316KB，13 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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FM25640C-G Overview

Non-Volatile SRAM, 8KX8, CMOS, PDSO8

FM25640C-G Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Reach Compliance Code	compliant
JESD-30 code	R-PDSO-G8
memory density	65536 bit
Memory IC Type	NON-VOLATILE SRAM
memory width	8
Number of terminals	8
word count	8192 words
character code	8000
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Certification status	Not Qualified
Maximum standby current	0.00001 A
Maximum slew rate	0.004 mA
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL

FM25640C-G Preview

Preliminary

FM25640C

64Kb Serial 5V F-RAM Memory

Features

64K bit Ferroelectric Nonvolatile RAM



Organized as 8,192 x 8 bits



High Endurance 1 Trillion (10

) Read/Writes



36 Year Data Retention at +75C



NoDelay™ Writes



Advanced high-reliability ferroelectric process

Very Fast Serial Peripheral Interface - SPI



Up to 20 MHz maximum bus frequency



Direct hardware replacement for EEPROM



SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)

Sophisticated Write Protection Scheme



Hardware Protection



Software Protection

Low Power Consumption



250

A

Active Current (1 MHz)



A

(typ.) Standby Current

Industry Standard Configuration



Industrial Temperature -40C to +85C



8-pin “Green”/RoHS SOIC (-G)

Description

The FM25640C is a 64-kilobit nonvolatile memory

employing an advanced ferroelectric process. A

ferroelectric random access memory or F-RAM is

nonvolatile but operates in other respects as a RAM.

It provides reliable data retention for 36 years while

eliminating the complexities, overhead, and system

level reliability problems caused by EEPROM and

other nonvolatile memories.

The FM25640C performs write operations at bus

speed. No write delays are incurred. Data is written to

the memory array immediately after it has been

successfully transferred to the device. The next bus

cycle may commence immediately without the need

for data polling. The FM25640C is capable of

supporting up to 10

read/write cycles, or a million

times more write cycles than EEPROM.

These capabilities make the FM25640C ideal for

nonvolatile memory applications requiring frequent

or rapid writes. Examples range from data collection,

where the number of write cycles may be critical, to

demanding industrial controls where the long write

time of EEPROM can cause data loss.

The FM25640C provides substantial benefits to users

of serial EEPROM, in a hardware drop-in

replacement. The FM25640C uses the high-speed SPI

bus, which enhances the high-speed write capability

of F-RAM technology. The specifications are

guaranteed over an industrial temperature range of

-40°C to +85°C.

Pin Configuration

VSS

VDD

HOLD

SCK

Pin Names

/CS

/HOLD

/WP

SCK

VDD

VSS

Function

Chip Select

Hold

Write Protect

Serial Clock

Serial Data Input

Serial Data Output

Ground

Ordering Information

FM25640C-G

FM25640C-GTR

“Green”/RoHS 8-pin SOIC

“Green”/RoHS 8-pin SOIC,

Tape & Reel

This is a product that has fixed target specifications but are subject

to change pending characterization results.

Rev. 1.1

June 2011

Ramtron International Corporation

1850 Ramtron Drive, Colorado Springs, CO 80921

(800) 545-F-RAM, (719) 481-7000

www.ramtron.com

Page 1 of 13

FM25640C - 64Kb 5V SPI F-RAM

HOLD

SCK

Instruction Decode

Clock Generator

Control Logic

Write Protect

1,024 x 64

FRAM Array

Instruction Register

Address Register

Counter

Data I/O Register

Nonvolatile Status

Figure 1. Block Diagram

Pin Description

Pin Name

/CS

I/O

Input

Pin Description

Chip Select: Enables and disables the device. When /CS is high, the output pin SO is hi-

Z, all other inputs are ignored, and the device remains in a low-power standby mode.

When /CS is low, the part will respond to the SCK signal. A falling edge on /CS must

occur for every op-code.

Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the

rising edge and outputs occur on the falling edge. The device is static so the clock

frequency may be any value between 0 and 20 MHz and may be interrupted at any time.

Hold: The /HOLD signal is used when the host CPU must interrupt a memory operation

for another task. Asserting the /HOLD signal low pauses the current operation. The

device ignores SCK and /CS. All transitions on /HOLD must occur while SCK is low.

Write Protect: This pin prevents write operations to the status register. This is critical

since other write protection features are controlled through the status register. A

complete explanation of write protection is provided below. *Note that the function of

/WP is different from the FM25040 where it prevents all writes to the part.

Serial Input: SI is the data input pin. It is sampled on the rising edge of SCK and is

ignored otherwise. It should always be driven to a valid logic level to meet IDD

specifications.

* SI may be connected to SO for a single pin data interface.

Serial Output: SO is the data output pin. It is driven during read cycles and remains hi-Z

at all other times including when HOLD\ is low. Data transitions are driven on the falling

edge of the serial clock.

* SO can be connected to SI for a single pin data interface since the part communicates

in half-duplex.

Supply Voltage: 5V

Ground

SCK

Input

/HOLD

Input

/WP

Input

Output

VDD

VSS

Supply

Rev. 1.1

June 2011

2 of 13

FM25640C - 64Kb 5V SPI F-RAM

Overview

The FM25640C is a serial F-RAM memory. The

memory array is logically organized as 8,192 x 8 and

is accessed using an industry standard Serial

Peripheral Interface or SPI bus. Functional operation

of the F-RAM is similar to serial EEPROMs. The

major difference between the FM25640C and a serial

EEPROM with the same pinout relates to its superior

write performance.

Serial Peripheral Interface – SPI Bus

The FM25640C employs a Serial Peripheral Interface

(SPI) bus. It is specified to operate at speeds up to 20

MHz. This high-speed serial bus provides high

performance serial communication to a host

microcontroller. Many common microcontrollers

have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary

port pins for microcontrollers that do not. The

FM25640C operates in SPI Mode 0 and 3.

The SPI interface uses a total of four pins: clock,

data-in, data-out, and chip select. It is possible to

connect the two data lines together. Figure 2

illustrates a typical system configuration using the

FM25640C with a microcontroller that offers an SPI

port. Figure 3 shows a similar configuration for a

microcontroller that has no hardware support for the

SPI bus.

Protocol Overview

The SPI interface is a synchronous serial interface

using clock and data lines. It is intended to support

multiple devices on the bus. Each device is activated

using a chip select. Once chip select is activated by

the bus master, the FM25640C will begin monitoring

the clock and data lines. The relationship between the

falling edge of /CS, the clock, and data is dictated by

the SPI mode. The device will make a determination

of the SPI mode on the falling edge of each chip

select. While there are four such modes, the

FM25640C supports modes 0 and 3. Figure 4 shows

the required signal relationships for modes 0 and 3.

In both cases, data is clocked into the FM25640C on

the rising edge of SCK and data is expected on the

first rising edge after /CS goes active. If the clock

begins from a high state, it will fall prior to beginning

data transfer in order to create the first rising edge.

The FM25640C is controlled by SPI op-codes. These

op-codes specify the commands to the part. After /CS

is asserted, the first byte transferred from the bus

master is the op-code. Following the op-code,

addresses and data are then transferred. Note that the

WREN and WRDI op-codes are commands with no

subsequent data transfer.

Important: The /CS must go inactive after an

operation is complete and before a new op-code

can be issued. There is one valid op-code only per

active chip select.

Memory Architecture

When accessing the FM25640C, the user addresses

8,192 locations of 8 data bits each. These data bits

are shifted in and out serially. The addresses are

accessed using the SPI protocol, which includes a

chip select (to permit multiple devices on the bus), an

op-code and a two-byte address. The upper 3 bits of

the address range are ignored by the device. The

complete address of 13-bits specifies each byte

address uniquely.

Most functions of the FM25640C either are

controlled by the SPI interface or are handled

automatically by on-board circuitry. The access time

for memory operation essentially is zero, beyond the

time needed for the serial protocol. That is, the

memory is read or written at the speed of the SPI bus.

Unlike an EEPROM, it is not necessary to poll the

device for a ready condition since writes occur at bus

speed. That is, by the time a new bus transaction can

be shifted into the part, a write operation will be

complete. This is explained in more detail in the

interface section.

Users expect several obvious system benefits from

the FM25640C due to its fast write cycle and high

endurance as compared with EEPROM. However

there are less obvious benefits as well. For example

in a high noise environment, the fast-write operation

is less susceptible to corruption than an EEPROM

since it is completed quickly. By contrast, an

EEPROM requiring milliseconds to write is

vulnerable to noise during much of the cycle.

Note that the FM25640C contains no power

management circuits other than a simple internal

power-on reset. It is the user’s responsibility to

ensure that V

is within datasheet tolerances to

prevent incorrect operation. It is recommended

that the part is not powered down with chip

enable active.

Rev. 1.1

June 2011

3 of 13

FM25640C - 64Kb 5V SPI F-RAM

SCK

MOSI

MISO

SI SCK

SPI

Microcontroller

SS1

SS2

HOLD1

HOLD2

MOSI: Master Out, Slave In

MISO: Master In, Slave Out

SS: Slave Select

FM25640C

HOLD

FM25640C

HOLD

Figure 2. System Configuration with SPI port

Microcontroller

SI SCK

FM25640C

HOLD

Figure 3. System Configuration without SPI port

SPI Mode 0: CPOL=0, CPHA=0

SPI Mode 3: CPOL=1, CPHA=1

Figure 4. SPI Modes 0 & 3

Rev. 1.1

June 2011

4 of 13

FM25640C - 64Kb 5V SPI F-RAM

Data Transfer

All data transfers to and from the FM25640C occur

in 8-bit groups. They are synchronized to the clock

signal (SCK) and they transfer most significant bit

(MSB) first. Serial inputs are registered on the rising

edge of SCK. The SO output is driven from the

falling edge of SCK.

Command Structure

There are six commands called op-codes that can be

issued by the bus master to the FM25640C. They are

listed in the table below. These op-codes control the

functions performed by the memory. They can be

divided into three categories. First, there are

commands that have no subsequent operations. They

perform a single function such as to enable a write

operation. Second are commands followed by one

byte, either in or out. They operate on the status

memory transactions followed by an address and one

or more bytes of data.

Table 1. Op-code Commands

Name

Description

WREN

WRDI

RDSR

WRSR

READ

WRITE

Set Write Enable Latch

Write Disable

Read Status Register

Write Status Register

Read Memory Data

Write Memory Data

WREN - Set Write Enable Latch

The FM25640C will power up with writes disabled.

The WREN command must be issued prior to any

write operation. Sending the WREN op-code will

allow the user to issue subsequent op-codes for

write operations. These include writing the status

Sending the WREN op-code causes the internal

Write Enable Latch to be set. A flag bit in the status

WEL=1 indicates that writes are permitted.

Attempting to write the WEL bit in the status

operation will automatically clear the write-enable

latch and prevent further writes without another

WREN command. Figure 5 illustrates the WREN

command bus configuration.

WRDI - Write Disable

The WRDI command disables all write activity by

clearing the Write Enable Latch. The user can verify

that writes are disabled by reading the WEL bit in

the status register and verifying that WEL=0. Figure

6 illustrates the WRDI command bus configuration.

Op-code value

0000_0110b

0000_0100b

0000_0101b

0000_0001b

0000_0011b

0000_0010b

Figure 5. WREN Bus Configuration

Figure 6. WRDI Bus Configuration

Rev. 1.1

June 2011

5 of 13

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