Am29LV652D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
24961
Revision
A
Amendment
+4
Issue Date
October 29, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
Am29LV652D
128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileIO™ Control
DISTINCTIVE CHARACTERISTICS
■
Two 64 Megabit (Am29LV065D) in a single 63-ball 11
x 12 mm FBGA package (Note: Features will be
described for each internal Am29LV065D)
■
Two Chip Enable inputs
— Each CE# controls selection of one internal
Am29LV065D device
■
Single power supply operation
— 3.0 to 3.6 volt read, erase, and program operations
■
VersatileIO™ control
— Device generates output voltages and tolerates input
voltages on DQ I/Os as determined by the voltage on
V
IO
input
■
High performance
— Access times as fast as 90 ns
■
Manufactured on 0.23 µm process technology
■
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
■
Ultra low power consumption (typical values at 3.0 V,
5 MHz) for the part
— 9 mA typical active read current
— 26 mA typical erase/program current
— 400 nA typical standby mode current
■
Flexible sector architecture
— Two hundred fifty-six 64 Kbyte sectors
■
Sector Protection
— A hardware method to lock a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
■
Compatibility with JEDEC standards
— Except for the added CE2#, the FBGA is pinout and
software compatible with single-power supply Flash
— Superior inadvertent write protection
■
Minimum 1 million erase cycle guarantee per sector
■
63-ball FBGA Package
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
■
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
■
Ready/Busy# output (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
■
Hardware reset input (RESET#)
— Hardware method to reset the device for reading array
data
■
ACC input
— Accelerates programming time for higher throughput
during system production
■
Program and Erase Performance (V
HH
not applied to
the ACC input)
— Byte program time: 5 µs typical
— Sector erase time: 1.6 s typical for each 64 Kbyte
sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
24961
Rev:
A
Amendment/+4
Issue Date:
October 29, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV652D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6
V) single power supply flash memory device organized
as two Am29LV065D dice in a single 63-ball FBGA
package. Each Am29LV065D is a 64 Mbit, 3.0 Volt
(3.0 V to 3.6 V) single power supply flash memory de-
vice organized as 8,388,608 bytes. Data appears on
DQ0-DQ7. The device is designed to be programmed
in-system with the standard system 3.0 volt V
CC
sup-
ply. A 12.0 volt V
PP
is not required for program or
erase operations. The Am29LV652D is equipped with
two CE#s for flexible selection between the two inter-
nal 64 Mb devices. The device can also be pro-
grammed in standard EPROM programmers.
The Am29LV652D offers access times of 90 and 120
ns and is offered in a 63-ball FBGA package. To elimi-
nate bus contention the Am29LV652D device contains
two separate chip enables (CE# and CE2#). Each chip
enable (CE# or CE2#) is connected to only one of the
two dice in the Am29LV652D package.
To the sys-
tem, this device is the same as two independent
Am29LV065D on the same board. The only differ-
ence is that they are now packaged together to re-
duce board space.
Each device requires only a
single 3.0 Volt power
supply
(3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on
V
IO
. This allows the device to operate in a 3 V or 5 V
system environment as required. For voltage levels
below 3 V, contact an AMD representative for more in-
formation.
The host system can detect whether a program or
erase operation is complete by observing RY/BY#, by
reading the DQ7 (Data# Polling), or DQ6 (toggle)
sta-
tus bits.
After a program or erase cycle is completed,
the device is ready to read array data or accept an-
other command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET#
terminates any operation in
progress and resets the internal state machine to
reading array data. RESET# may be tied to the system
reset circuitry. A system reset would thus also reset
the device, enabling the system microprocessor to
read boot-up firmware from the Flash memory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The
accelerated program (ACC)
feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH
, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
2
Am29LV652D
October 29, 2004
P R E L I M I N A R Y
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV652D Device Bus Operations ................................9
Table 10. Am29LV652D Command Definitions ............................. 30
Write Operation Status . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 5. Data# Polling Algorithm .................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 6. Toggle Bit Algorithm........................................................ 32
VersatileIO
™
(V
IO
) Control ....................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation .......................................... 10
Autoselect Functions ........................................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table for CE# ..........................................11
Table 3. Sector Address Table for CE2# ........................................15
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 11. Write Operation Status ................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform ..................... 35
Figure 8. Maximum Positive Overshoot Waveform....................... 35
DC Characteristics (for two Am29LV065 devices)
36
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 37
Figure 10. Typical I
CC1
vs. Frequency ............................................ 37
Figure 11. Test Setup.................................................................... 38
Table 12. Test Specifications ......................................................... 38
Figure 12. Input Waveforms and Measurement Levels ................. 38
Autoselect Mode ..................................................................... 19
Table 4. Am29LV652D Autoselect Codes, (High Voltage Method) 19
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Sector Group Protection and Unprotection ............................. 20
Table 5. Sector Group Protection/Unprotection Address Table .....20
Temporary Sector Group Unprotect ....................................... 21
Figure 1. Temporary Sector Group Unprotect Operation................ 21
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 22
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 13. Read Operation Timings ............................................... 39
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit ......................................................... 23
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 6. CFI Query Identification String ..........................................
System Interface String...................................................................
Table 8. Device Geometry Definition ..............................................
Table 9. Primary Vendor-Specific Extended Query ........................
23
24
24
25
Hardware Reset (RESET#) .................................................... 40
Figure 14. Reset Timings ............................................................... 40
Erase and Program Operations .............................................. 41
Figure 15. Program Operation Timings..........................................
Figure 16. Accelerated Program Timing Diagram..........................
Figure 17. Chip/Sector Erase Operation Timings ..........................
Figure 18. Data# Polling Timings (During Embedded Algorithms).
Figure 19. Toggle Bit Timings (During Embedded Algorithms)......
Figure 20. DQ2 vs. DQ6.................................................................
42
42
43
44
45
45
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................ 25
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Byte Program Command Sequence ....................................... 26
Unlock Bypass Command Sequence .................................. 26
Figure 3. Program Operation .......................................................... 27
Temporary Sector Unprotect .................................................. 46
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 46
Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 47
Figure 23. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 49
Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 28
Figure 4. Erase Operation............................................................... 29
Erase And Programming Performance . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FSA063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm
package .................................................................................. 51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
October 29, 2004
Am29LV652D
3
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