V62C1884096LL-100BI datasheet, PDF

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V62C1884096LL-100BI: DescriptionStandard SRAM, 512KX8, 100ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36; Categorystorage storage; File Size47KB，10 Pages; ManufacturerMosel Vitelic Corporation ( MVC ); Websitehttp://www.moselvitelic.com

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V62C1884096LL-100BI Overview

Standard SRAM, 512KX8, 100ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36

V62C1884096LL-100BI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Mosel Vitelic Corporation ( MVC )
Parts packaging code	BGA
package instruction	TFBGA, BGA36,6X8,30
Contacts	36
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	100 ns
I/O type	COMMON
JESD-30 code	R-PBGA-B36
JESD-609 code	e0
length	10 mm
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	36
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA36,6X8,30
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.000002 A
Minimum standby current	1 V
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	2.3 V
Minimum supply voltage (Vsup)	1.8 V
Nominal supply voltage (Vsup)	2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm

V62C1884096LL-100BI Preview

MOSEL VITELIC

V62C1884096

512K X 8, CMOS STATIC RAM

PRELIMINARY

Features

High-speed: 85, 100 ns

Ultra low standby current of 2

A (max.)

Fully static operation

All inputs and outputs directly compatible

Three state outputs

Ultra low data retention current (V

= 1.0V)

Operating voltage: 1.8V–2.3V

Packages

– 36-Ball CSP BGA (8mm x 10mm)

Description

The V62C1884096 is a very low power CMOS

static RAM organized as 524,288 words by 8 bits.

Easy memory expansion is provided by an active

LOW CE1, and active HIGH CE2, an active LOW

OE, and three static I/O’s. This device has an

automatic power-down mode feature when

deselected.

Functional Block Diagram

Input Buffer

Row Decoder

Sense Amp

I/O

1024

4096

I/O1

Column Decoder

Control

Circuit

CE1

CE2

Device Usage Chart

Operating

Temperature

Range

C to 70

–40

C to +85

Package

Outline

•

Access Time (ns)

•

100

•

Power

•

Temperature

Mark

Blank

V62C1884096 Rev. 1.2 June 2000

MOSEL VITELIC

Pin Descriptions

–A

Address Inputs

These 19 address inputs select one of the 512K x 8

bit segments in the RAM.

, CE

Chip Enable Inputs

is active LOW and CE

is active HIGH. Both

chip enables must be active to read from or write to

the device. If either chip enable is not active, the

device is deselected and is in a standby power

mode. The I/O pins will be in the high-impedance

state when deselected.

Output Enable Input

The Output Enable input is active LOW. With chip

enabled, when OE is LOW and WE HIGH, data of

the selected memory location will be available on

the I/O pins. When OE is HIGH, the I/O pins will be

in the high impedance state.

V62C1884096

Write Enable Input

The write enable input is active LOW and controls

read and write operations. With the chip enabled,

when WE is HIGH and OE is LOW, output data will

be present at the I/O pins; when WE is LOW and

OE is HIGH, the data present on the I/O pins will be

written into the selected memory locations.

I/O

–I/O

Data Input and Data Output Ports

These 8 bidirectional ports are used to read data

from and write data into the RAM.

GND

Power Supply

Ground

Pin Configurations (Top View)

36 BGA

I/O5

I/O6

VSS

VCC

I/O7

I/O8

A10

CE2

A18

CE1

A11

A17

A16

A12

A15

A13

I/O1

I/O2

VCC

VSS

I/O3

I/O4

A14

Note:

NC means no connect.

NB means no ball.

TOP VIEW

V62C1884096 Rev. 1.2 June 2000

MOSEL VITELIC

Part Number Information

MOSEL-VITELIC

MANUFACTURED

V62C1884096

4096

–

TEMP.

SRAM

FAMILY

OPERATING

VOLTAGE

DENSITY

PWR.

4096K

SPEED

85 ns

100 ns

PKG

BLANK = 0°C to 70°C

I = -40°C to +85°C

62 = STANDARD

C = CMOS PROCESS

18 = 1.8V–2.3V

T = TSOP STANDARD

B = BGA

ORGANIZATION

8 = 8-bit

L = LOW POWER

LL = LOW LOW POWER

Absolute Maximum Ratings

(1)

Symbol

BIAS

STG

Parameter

Supply Voltage

Input Voltage

Input/Output Voltage Applied

Temperature Under Bias

Storage Temperature

Commercial

-0.5 to + V

+ 0.5

-0.5 to + V

+ 0.5

+ 0.3

-10 to +125

-55 to +125

Industrial

-0.5 to + V

+ 0.5

-0.5 to + V

+ 0.5

+ 0.3

-65 to +135

-65 to +150

Units

NOTE:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Capacitance*

= 25

C, f = 1.0MHz

Symbol

OUT

Parameter

Input Capacitance

Output Capacitance

Conditions

= 0V

I/O

= 0V

Max.

Unit

Truth Table

Mode

Standby

Output Disable

Read

Write

I/O

Operation

High Z

OUT

NOTE:

1. This parameter is guaranteed and not tested.

NOTE:

X = Don’t Care, L = LOW, H = HIGH

V62C1884096 Rev. 1.2 June 2000

MOSEL VITELIC

DC Electrical Characteristics

(over all temperature ranges, V

= 1.8V–2.3V)

Symbol

V62C1884096

Parameter

Input LOW Voltage

(1,2)

Input HIGH Voltage

(1)

Input Leakage Current

Output Leakage Current

Output LOW Voltage

Output HIGH Voltage

Test Conditions

Min.

-0.3

1.6

Typ.

—

Max.

0.4

+0.3

0.4

—

Units

= Max, V

= 0V to V

= Max, CE

= V

, V

OUT

= 0V to V

= Min, I

= 2mA

= Min, I

= -0.5mA

—

–0.4

Symbol

CC1

Parameter

Average Operating Current, CE

= V

, CE

= V

– 0.2, Output Open,

= Max.

TTL Standby Current

≥

, CE

≤

, V

= Max., f = 0

CMOS Standby Current, CE

≥

– 0.2V, CE

≤

0.2V,

≥

– 0.2V or V

≤

0.2V, V

= Max., f = 0

f = fmax

f = 1 MHz

Comm.

(3)

0.4

0.3

Ind.

(3)

0.5

0.3

Units

SB1

µA

NOTES:

1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2. V

(Min.) = -3.0V for pulse width < t

/2.

3. Maximum value.

AC Test Conditions

Input Pulse Levels

Input Rise and Fall Times

Timing Reference Levels

Output Load

0 to 1.6V

5 ns

0.9V

see below

AC Test Loads and Waveforms

TTL

= 30pF + 1TTL Load

* Includes scope and jig capacitance

V62C1884096 Rev. 1.2 June 2000

MOSEL VITELIC

Data Retention Characteristics

Symbol

V62C1884096

Parameter

for Data Retention

≥

– 0.2V, CE

< 0.2V, V

≥

– 0.2V,

or V

≤

0.2V

Data Retention Current

≥

– 0.2V, CE

< 0.2V, V

≥

– 0.2V,

or V

≤

0.2V, V

= 1.0V

Com’l

Power

Min.

1.0

Typ.

(2)

—

Max.

2.3

Units

CCDR

—

RC(1)

0.5

—

1.5

—

µA

Ind.

CDR

Chip Deselect to Data Retention Time

Operation Recovery Time (see Retention Waveform)

NOTES:

1. t

= Read Cycle Time

2. T

= +25°C.

Low V

Data Retention Waveform (1) (CE

Controlled)

Data Retention Mode

1.8V

CDR

1.6V

≥

– 0.2V

≥

1.6V

1.8V

Key to Switching Waveforms

WAVEFORM

INPUTS

MUST BE

STEADY

MAY CHANGE

FROM H TO L

OUTPUTS

WILL BE

STEADY

WILL BE

CHANGING

FROM H TO L

WILL BE

CHANGING

FROM L TO H

CHANGING:

STATE

UNKNOWN

CENTER

LINE IS HIGH

IMPEDANCE

“OFF” STATE

MAY CHANGE

FROM L TO H

DON'T CARE:

ANY CHANGE

PERMITTED

DOES NOT

APPLY

V62C1884096 Rev. 1.2 June 2000

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Description	Standard SRAM, 512KX8, 100ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36	Standard SRAM, 512KX8, 85ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36	Standard SRAM, 512KX8, 100ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36	Standard SRAM, 512KX8, 85ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36	Standard SRAM, 512KX8, 85ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36	Standard SRAM, 512KX8, 100ns, CMOS, PBGA36, 8 X 10 MM, CSP, BGA-36
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	TFBGA, BGA36,6X8,30	TFBGA, BGA36,6X8,30	TFBGA, BGA36,6X8,30	TFBGA, BGA36,6X8,30	TFBGA, BGA36,6X8,30	TFBGA, BGA36,6X8,30
Contacts	36	36	36	36	36	36
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	100 ns	85 ns	100 ns	85 ns	85 ns	100 ns
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B36	R-PBGA-B36	R-PBGA-B36	R-PBGA-B36	R-PBGA-B36	R-PBGA-B36
JESD-609 code	e0	e0	e0	e0	e0	e0
length	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm
memory density	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1
Number of terminals	36	36	36	36	36	36
word count	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words
character code	512000	512000	512000	512000	512000	512000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C	70 °C	70 °C
organize	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA36,6X8,30	BGA36,6X8,30	BGA36,6X8,30	BGA36,6X8,30	BGA36,6X8,30	BGA36,6X8,30
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2 V	2 V	2 V	2 V	2 V	2 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum standby current	0.000002 A	0.000003 A	0.0000015 A	0.000002 A	0.0000015 A	0.000003 A
Minimum standby current	1 V	1 V	1 V	1 V	1 V	1 V
Maximum slew rate	0.03 mA	0.025 mA	0.025 mA	0.03 mA	0.025 mA	0.025 mA
Maximum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Minimum supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Nominal supply voltage (Vsup)	2 V	2 V	2 V	2 V	2 V	2 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.75 mm	0.75 mm	0.75 mm	0.75 mm	0.75 mm	0.75 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm

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