XPC603PRX266LX datasheet, PDF - EEWORLD Datasheet

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XPC603PRX266LX: Description32-BIT, 266MHz, RISC PROCESSOR, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255; CategoryThe embedded processor and controller Microcontrollers and processors; File Size552KB，36 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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XPC603PRX266LX Overview

32-BIT, 266MHz, RISC PROCESSOR, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255

XPC603PRX266LX Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	BGA,
Contacts	255
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	75 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B255
length	21 mm
low power mode	YES
Number of terminals	255
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3 mm
speed	266 MHz
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Freescale Semiconductor, Inc.

Semiconductor Products Sector

Order Number: MPC603E7TEC/D

Rev. 4, 5/2000

Freescale Semiconductor, Inc...

Technical Data

PowerPC

603e RISC Microprocessor Family:

PID7t-603e Hardware SpeciÞcations

The PowerPC 603eª microprocessor is an implementation of the PowerPC family of reduced instruction

set computing (RISC) microprocessors. In this document, the term Ô603eÕ is used as an abbreviation for the

PowerPC 603e microprocessor. The PowerPC 603e microprocessors are available from Motorola as

MPC603e.

The 603e is implemented in several semiconductor fabrication processes. Different processes may require

different supply voltages and may have other electrical differences but will have the same functionality. As

a technical designator to distinguish between 603e implementations in various processes, a preÞx composed

of the processor version register (PVR) value and a process identiÞer (PID) is assigned to the various

implementations as shown below:

Table 1PowerPC 603e Microprocessors from Motorola

Technical

Designator

PID6-603e

PID7v-603e

PID7t-603e

Process

0.5 µm CMOS, 4LM

0.35 µm CMOS, 5LM

0.29 µm CMOS, 5LM

Core

Voltage

3.3 V

2.5 V

I/O

Voltage

3.3 V

5-Volt

Tolerant

Yes

Part Number

MPC603E

XPC603P (end-of-life)

MPC603R

This document contains information on a new product under development by Motorola.

Motorola reserves the right to change or discontinue this product without notice.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Overview

This document describes the pertinent physical characteristics of the PID7t-603e from Motorola. For

functional characteristics of the 603e, refer to the

PowerPC 603e RISC Microprocessor UserÕs Manual

This document contains the following topics:

Topic

Page

Freescale Semiconductor, Inc...

Section 1.1, ÒOverviewÓ

Section 1.2, ÒFeaturesÓ

Section 1.3, ÒGeneral ParametersÓ

Section 1.4, ÒElectrical and Thermal CharacteristicsÓ

Section 1.5, ÒPin AssignmentsÓ

Section 1.6, ÒPinout ListingsÓ

Section 1.7, ÒPackage DescriptionsÓ

Section 1.8, ÒSystem Design InformationÓ

Section 1.9, ÒOrdering InformationÓ

To locate any published errata or updates for this document, refer to the website at

http://www.motorola.com/semiconductors.

1.1 Overview

This section describes the features of the 603e and describes brießy how those units interact.

The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set

computing (RISC) microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture

speciÞcation, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and

ßoating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture

provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit

architecture.

The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and

sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.

The fourth is a dynamic power management mode that causes the functional units in the 603e to

automatically enter a low-power mode when the functional units are idle without affecting operational

performance, software execution, or any external hardware.

The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock.

Instructions can execute out of order for increased performance; however, the 603e makes completion

appear sequential.

The 603e integrates Þve execution unitsÑan integer unit (IU), a ßoating-point unit (FPU), a branch

processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute Þve

instructions in parallel and the use of simple instructions with rapid execution times yield high efÞciency

and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is

pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches

for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs

contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and

ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block

translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e also

PID7t-603e Hardware Specifications

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Features

supports block address translation through the use of two independent instruction and data block address

translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously

with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,

if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.

The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows

multiple masters to compete for system resources through a central external arbiter. The 603e provides a

three-state coherency protocol that supports the exclusive, modiÞed, and invalid cache states. This protocol

is a compatible subset of the MESI (modiÞed/exclusive/shared/invalid) four-state protocol and operates

coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers

for memory accesses, and supports memory-mapped I/O.

The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility

with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The CBGA package

supports speed bins of 200 MHz, 266 MHz, and 300 MHz. The PBGA package is a pin-compatible drop in

replacement for the CBGA; however this package only supports speeds up to 200 MHz.

Freescale Semiconductor, Inc...

1.2 Features

This section summarizes features of the 603eÕs implementation of the PowerPC architecture. Major features

of the 603e are as follows:

High-performance, superscalar microprocessor

Ñ As many as three instructions issued and retired per clock

Ñ As many as Þve instructions in execution per clock

Ñ Single-cycle execution for most instructions

Ñ Pipelined FPU for all single-precision and most double-precision operations

Five independent execution units and two register Þles

Ñ BPU featuring static branch prediction

Ñ A 32-bit IU

Ñ Fully IEEE 754-compliant FPU for both single- and double-precision operations

Ñ LSU for data transfer between data cache and GPRs and FPRs

Ñ SRU that executes condition register (CR), special-purpose register (SPR) instructions, and

integer add/compare instructions

Ñ Thirty-two GPRs for integer operands

Ñ Thirty-two FPRs for single- or double-precision operands

High instruction and data throughput

Ñ Zero-cycle branch capability (branch folding)

Ñ Programmable static branch prediction on unresolved conditional branches

Ñ Instruction fetch unit capable of fetching two instructions per clock from the instruction cache

Ñ A six-entry instruction queue that provides lookahead capability

Ñ Independent pipelines with feed-forwarding that reduces data dependencies in hardware

Ñ 16-Kbyte data cacheÑfour-way set-associative, physically addressed; LRU replacement

algorithm

PID7t-603e Hardware Specifications

For More Information On This Product,

Go to: www.freescale.com

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