VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Features
• ANSI X3T11 Fibre Channel Compliant
• 1.0625Gb/s Operation
• Features the FibreTimer
™
Configurable Clock
Recovery Unit (CRU): Repeater, Retimer or
Bypassed
• Six Port Bypass Circuits (PBC)
•
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
Analog/Digital Signal Detect (SDU)
• On-Chip Transmit Termination
•
3.3V, 700mW Power Dissipation
• Compatible with HDMP-0451 (VSC7127) or
HDMP-0452 (VSC7129)
• 44-Pin, 10mm PQFP Package
General Description
The VSC7127 and VSC7129 contain six cascaded Port Bypass Circuits (PBCs), the FibreTimer
™
config-
urable Repeater/Retimer (CRU) and a Signal Detect Unit (SDU). These parts are typically used in distributing
Fibre Channel signals to an array of disk drives in an FC-AL loop as illustrated in Figure 1. The first
VSC7127’s CRU is configured as a Repeater to attenuate jitter, the second VSC7127’s CRU is bypassed to
reduce power and the third VSC7127’s CRU is configured as a retimer so that the output of the device is a jitter-
compliance point.
Each PBC is a multiplexer that is controlled by the corresponding SELx line which, if HIGH, selects the
external input or, if LOW, selects the output of the previous PBC. For the VSC712xR, when MODE is LOW
and SEL5 is HIGH, the CRU is a sophisticated repeater which has low latency, no peaking and attenuates jitter
even at low frequencies. When MODE is HIGH and SEL5 is HIGH, the CRU is a retimer which eliminates jit-
ter transfer but has increased latency due to an elasticity buffer which adds/drops Fibre Channel fill words in
order to accomodate the difference between the baud rate of the incoming data and the local REFCLK. When
SEL5 is LOW, the CRU is bypassed and powered down. The SDU monitors the analog levels of the IO+/- input
and monitors the output of the CRU digitally to indicate whether valid data is present.
The VSC7127/VSC7129 are similar to the VSC7124 which does not contain the FibreTimer
™
cell or CMU.
VSC7127/VSC7129 Block Diagram
O1+
O1-
I1+
I1-
SEL1
O2+
O2-
I2+
I2-
SEL2
O3+
O3-
I3+
I3-
SEL3
O4+
O4-
I4+
I4-
SEL4
O0+
O0-
I0+
I0-
SEL0
1
0
REFCLK
106.25MHz
CMU
1
0
1
0
1
0
1
0
0.1uF
PBC1
SEL5
1
0
PBC2
PBC3
PBC4
PBC0
PBC5
CRU
MODE
SDU
SIGDET
G52298-0, Rev 4.3
05/01/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Application: Fibre Channel Disk Arrays
A 12-port JBOD is shown in Figure 1. This dual loop application uses 3 VSC7127Xs on each loop in order
to configure the FC-AL disk array. Functional drives are included in the FC-AL loop while non-functional or
missing drives (numbers 2, 7, 9) are excluded.
Figure 1: 12-Drive FC-AL JBOD Application
Optics
or
Copper
1
LOOP A
Retimer
0
1
Retimer
0
1
0
VSC7127T #6
7125
SerDes
7125
SerDes
1
VSC7127T #5
0
1
2
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
0
1
4
VSC7121 QUAD PORT BYPASS CIRCUIT
0
1
3
4
0
1
3
0
1
VSC7127R #4
CONFIGURATION:
7127R #1 & 2: Repeater Mode
SEL0=1, SEL5=1
MODE=0
7127R #3 & 4: Bypass Mode
SEL5=0
MODE=x, No REFCLK
7127T #5 & 6: Retimer Mode
SEL1=1, SEL5=1
MODE=1
0
1
1
0
2
0
4
1
5
6
0
1
VSC7127 R#3
0
1
0
1
3
0
1
7
7125
SerDes
7125
SerDes
0
1
2
0
1
8
0
1
0
0
1
0
1
9
0
1
4
0
1
VSC7127R #2
0
1
3
VSC7127R #1
0
1
0
1
2
0
1
Optics
or
Copper
0
1
1
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
7125
SerDes
10
11
12
LOOP B
Repeater
0
Repeater
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52298-0, Rev 4.3
05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Functionality
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
Device Configurations
Four devices are specified in this datasheet: VSC7127R, VSC7127T, VSC7129R and VSC7129T. The
VSC7127 is pin-compatible to the HDMP-0451. The VSC7129 is pin compatible with the HDMP-0452. The
VSC712xR is configured as a Repeater when pin 12, MODE, is LOW, or a Retimer when HIGH. The
VSC712xT is configured as a Retimer when pin 12, MODE, is LOW, or a Repeater when HIGH.
Port Bypass Circuits
The VSC712x contains six Port Bypass Circuits (PBCs) which are 2-to-1 multiplexers used to steer serial
signals. Each PBC, PBCx has a single select line, SELx, which when HIGH, selects the external input, Ix, to
PBCx and when LOW, selects the output of the previous PBC. PCB5 does not have an external input but selects
between the output of the CRU (when SEL5 is HIGH) and the output of PBC0 (when SEL5 is LOW). These
controls allow FC-AL loops to include a functional device on the loop or exclude a non-functional device from
the loop.
FibreTimer
™
Clock Recovery Unit—Repeater Mode
The Clock Recovery Unit (CRU) is a digital PLL which extracts the clock from the incoming data and sam-
ples the data with the extracted clock. In repeater mode, the output of the CRU is synchronized to the recovered
clock and has improved signal quality due to amplification of the signal and attenuation of jitter. Latency
through the device is quite low, just a few bit times. Multiple repeaters can be cascaded without accumulation
of jitter. MODE determines whether the CRU is a Repeater or a Retimer.
FibreTimer
™
Clock Recovery Unit —Retimer Mode
MODE may configure the CRU as a retimer where the recovered data is placed into an elasticity buffer.
Data is taken out of the elasticity buffer and retransmitted synchronously to the local REFCLK. For Fibre Chan-
nel data, Fill words will be added and dropped in the elasticity buffer in order to accomodate the differences in
speed between the incoming data and the REFCLK. The retimer does not transfer jitter from the input to the
output but has longer latency, up to 4 word times, through the device.
FibreTimer
™
Clock Recovery Unit—Bypass Mode
When SEL5 is LOW, PBC5 selects the output of PBC0 and the CRU is unused. In this mode, the CRU is
powered down to reduce power dissipation. If the part will be used only in this mode, REFCLK and MODE are
ignored and can be left open. If the CRU is bypassed, the Signal Detect Unit is disabled and the output is LOW.
Signal Detection
A signal detect unit (SDU) monitors IO+/- and the output of the CRU to determine if there is a valid Fibre
Channel signal present. The SIGDET is updated every 160 bits (an “interval”) with the previous interval’s status
of three different Signal Detect Units: analog signal amplitude (ASDU), run length check (RLLSDU), Ordered
Set density (OSSDU). If the input amplitude is less than 200mV (differential), ASDU will be set LOW. If the
input amplitude is greater than 400mV, ASDU will be asserted HIGH. If a run length violation occurs (more
than 5 consecutive ones or zeros), the RLLSDU will be set LOW and stay LOW until the occurrence of a valid
G52298-0, Rev 4.3
05/01/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
Data Sheet
VSC7127/VSC7129
Fill Word or Primitive Sequence. Any Fill Word or Primitive Sequence will reset the OSSDU counter which
will increment on any 160-bit sequence which is not a Fill Word or Primitive Sequence. If the counter reaches
256, a Fill Word or Primitive Sequence has not occured often enough so OSSDU is asserted until reset again.
SIGDET is just an or’ing of these three state machines resynchronized to the 160-bit interval clock.
If SEL5 is LOW or REFCLK is absent, the signal detect unit is disabled and SIGDET is LOW.
Application Example
Figure 2 shows one loop of an 8-drive JBOD implemented with two VSC712xs per loop. The input from
the connector goes through a repeater in order to clean up the signal prior to the array of disk drives. After all
eight PBCs, the output the to connector is retimed to ensure jitter compliance at the connector.
Figure 2: 8-Drive JBOD
Drive 2
O2
I2
1
0
SEL1
SEL2
Drive 3
O3
I3
Drive 5
O2
I2
SEL2
1
SEL3
0
SEL1
I1
O1
1 MODE
SEL0
1
Drive 6
O3
I3
SEL3
O4
0
1
Drive 4
Drive 1
O4
1
I1
O1
0
MODE
MODE=0
SEL0=1
0
1
I4
SEL4
MODE=1
SEL1=1
0
1
I4
SEL4
RPTR
1
0
O0
RTMR
0
O0
1 SEL0
I0
I0
Drive 8
NOT SHOWN: PBC5, SEL5
Connector
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Drive 7
G52298-0, Rev 4.3
05/01/01
0
1
1
0
1
0
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7127/VSC7129
Family of Repeater/Retimer and Port
Bypass Circuits for Fibre Channel
AC Characteristics
(Over Recommended Operating Conditions)
Figure 3: Timing Waveforms
Ix+/-
Ox+/-
T
1
T
1
Table 1: AC Characteristics
(Over recommended operating conditions)
Parameters
T
1
T
1
T
R
, T
F
T
j(PBC)
T
J(RPTR)
Description
Propagation delay (Repeater mode)
Propagation delay (Retimer mode)
Serial data rise and fall time
Data jitter accumulation
(PBC only)
Total data output jitter
(Repeater mode)
Serial data output deterministic jitter
(p-p) (Repeater mode)
Total data output jitter
(Retimer Mode)
(1)
Serial data output deterministic jitter
(p-p) (Retimer Mode)
(1)
Jitter tolerance
Min
Typ
Max
7.0
180
300
120
192
Units
ns
ns
ps
ps
ps
Conditions
Delay with all circuits bypassed.
Delay with all circuits bypassed.
Typical delay is 100 bit times.
At
∆
V
IN
minimum levels
Peak-to-peak on Ox+/- in Port
Bypass Circuit Mode.
Jitter generation at Ox+/- when
driven by the CRU in Repeater
Mode. IEEE 802.3z Clause 38.68
Jitter generation at Ox+/- when
driven by the CRU in Repeater
Mode. IEEE 802.3z Clause 38.68
Jitter generation at Ox+/- when
driven by the CRU in Retimer
Mode.
Jitter generation at Ox+/- when
driven by the CRU in Retimer
Mode.
Minimum eye opening for proper
operation as defined in MJS 8.0.
T
DJ(RPTR)
80
ps
T
J(RTMR)
192
ps
T
DJ(RTMR)
T
JTOL
80
0.24
ps
UI
NOTE: (1) Retimer mode is only available for Fibre Channel applications.
G52298-0, Rev 4.3
05/01/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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