2308B-4DC8 datasheet, PDF - EEWORLD Datasheet

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2308B-4DC8: DescriptionPLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, SOIC-16; Categorylogic logic; File Size282KB，17 Pages; ManufacturerIDT (Integrated Device Technology)

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2308B-4DC8 Overview

PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, SOIC-16

2308B-4DC8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	_compli
series	2308
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	9.9314 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.008 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	1.7272 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	3.937 mm
minfmax	133.3 MHz
Base Number Matches	1

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DATASHEET

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

Description

The IDT2308B is a high-speed phase-lock loop (PLL) clock

multiplier. It is designed to address high-speed clock

distribution and multiplication applications. The zero delay

is achieved by aligning the phase between the incoming

clock and the output clock, operable within the range of 10

to 133 MHz.

The IDT2308B has two banks of four outputs each that are

controlled via two select addresses. By proper selection of

input addresses, both banks can be put in tri-state mode. In

test mode, the PLL is turned off, and the input clock directly

drives the outputs for system testing purposes. In the

absence of an input clock, the IDT2308B enters power

down, and the outputs are tri-stated. In this mode, the

device will draw less than 25µA.

The IDT2308B is available in six unique configurations for

both prescaling and multiplication of the Input REF Clock.

(see Available Options table.)

The PLL is closed externally to provide more flexibility by

allowing the user to control the delay between the input

clock and the outputs.

IDT2308B

Features

•

Phase-Lock Loop Clock Distribution for Applications

ranging from 10 MHz to 133 MHz operating frequency

•

Distributes one clock input to two banks of four outputs

•

Separate output enable for each output bank

•

External feedback (FBK) pin is used to synchronize the

outputs to the clock input

•

Output Skew <200 ps

Low jitter <200 ps cycle-to-cycle

1x, 2x, 4x output options (see Available Options table)

No external RC network required

Operates at 3.3 V V

Available in 16-pin SOIC and TSSOP packages

Available in Commercial and Industrial temperature

ranges

Block Diagram

IDT™

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

IDT2308B

REV B 030509

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