Low Skew, 1-to-8 Differential-to-
3.3V LVPECL/ECL Fanout Buffer
ICS853S310I
DATA SHEET
General Description
The ICS853S310I is a low skew, high performance 1-to-8
Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx,
nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL
differential input levels. The ICS853S310I is characterized to operate
from a 3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S310I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
•
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•
•
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Eight differential 3.3V LVPECL/ECL outputs
Two selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLKx input
Output skew: 20ps (typical)
Propagation delay: 825ps (typical)
Additive phase jitter, RMS: 0.14ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 3.0V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.0V to -3.8V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) package
Block Diagram
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
CLK_SEL
Pulldown
V
BB
1
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
Q0
nQ0
Pin Assignment
V
CCO
nQ0
nQ1
nQ2
Q0
Q1
Q2
25 24 23 22 21 20 19
V
EE
CLK_SEL
PCLK0
V
CC
nPCLK0
V
BB
PCLK1
26
27
28
1
2
3
4
5
nPCLK1
18
17
16
15
14
13
12
6
nc
Q3
nQ3
Q4
V
CCO
nQ4
Q5
nQ5
7
nQ7
8
V
CCO
9
Q7
10 11
nQ6
Q6
Q5
nQ5
Q6
nQ6
Q7
nQ7
ICS853S310I
28-Lead PLCC
11.6mm x 11.4mm x 4.1
mm package body
V Package
Top View
ICS853S310CVI
REVISION A NOVEMBER 17, 2010
1
©2010 Integrated Device Technology, Inc.
ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 9
8, 15, 22
10, 11
12, 13
14, 16
17, 18
19, 20
21, 23
24, 25
26
27
28
Name
V
CC
nPCLK0
V
BB
PCLK1
nPCLK1
nc
nQ7, Q7
V
CCO
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
V
EE
CLK_SEL
PCLK0
Power
Input
Output
Input
Input
Unused
Output
Power
Output
Output
Output
Output
Output
Output
Output
Power
Input
Input
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Type
Description
Positive supply pin.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Bias voltage to be connected for single-ended applications.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
No connect
Differential output pair. LVPECL/ECL interface levels.
Output supply pins.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW,
selects PCLK0, nPCLK0 inputs. LVPECL single-ended interface levels. Also
accepts standard LVCMOS input levels.
Non-inverting differential LVPECL clock input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLDOWN
R
VCC/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
k
Ω
k
Ω
ICS853S310CVI
REVISION A NOVEMBER 17, 2010
2
©2010 Integrated Device Technology, Inc.
ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= V
CCO
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
± 0.5mA
-40°C to +85°C
50.4°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CCO
= 3.0V to 3.8V, V
EE
= 0V; T
A
= -40°C to 85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.8
3.8
65
Units
V
V
mA
Table 3B. ECL Power Supply DC Characteristics,
V
EE
= -3.8V to -3.0V, V
CC
= V
CCO
= 0V; T
A
= -40°C to 85°C
Symbol
V
EE
I
EE
Parameter
Supply Voltage
Power Supply Current
Test Conditions
Minimum
-3.0
Typical
-3.3
Maximum
-3.8
65
Units
V
mA
ICS853S310CVI
REVISION A NOVEMBER 17, 2010
3
©2010 Integrated Device Technology, Inc.
ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Table 3C. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.0V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Input High Voltage
(Single-ended); NOTE 2
Input Low Voltage
(Single-ended); NOTE 2
Output Voltage Reference
Peak-to-Peak
Input Voltage
Input High Voltage Common
Mode Range; NOTE 3
Input
High
Current
Input
Low
Current
PCLK[0:1],
nPCLK[0:1],
CLK_SEL
PCLK[0:1],
CLK_SEL
nPCLK[0:1]
-10
-150
Min
V
CC
- 1.15
V
CC
- 1.835
V
CC
- 1.225
V
CC
- 1.87
V
CC
- 1.44
150
1.2
Typ
V
CC
- 0.94
V
CC
- 1.73
Max
V
CC
- 0.86
V
CC
- 1.63
V
CC
- 0.94
V
CC
- 1.535
V
CC
- 1.30
1000
V
CC
Min
V
CC
- 1.14
V
CC
- 1.875
V
CC
- 1.225
V
CC
- 1.87
V
CC
- 1.44
150
1.2
25°C
Typ
V
CC
- 0.96
V
CC
- 1.75
Max
V
CC
- 0.88
V
CC
- 1.665
V
CC
- 0.94
V
CC
- 1.535
V
CC
- 1.30
1000
V
CC
Min
V
CC
- 1.13
V
CC
- 1.87
V
CC
- 1.225
V
CC
- 1.87
V
CC
- 1.44
150
1.2
85°C
Typ
V
CC
- 0.97
V
CC
- 1.765
Max
V
CC
- 0.89
V
CC
- 1.67
V
CC
- 0.94
V
CC
- 1.535
V
CC
- 1.30
1000
V
CC
Units
V
V
V
V
V
mV
V
I
IH
150
150
150
µA
-10
-150
-10
-150
µA
µA
I
IL
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
– 2V.
NOTE 2: Applies to CLK_SEL, PCLK0, nPCLK0, PCLK1, and nPCLK1 if connected to V
BB
per Figure 2.
NOTE 3: Common mode voltage is defined as V
IH
.
Table 3D. ECL DC Characteristics,
V
CC
= V
CCO
= 0V; V
EE
= -3.8V to -3.0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Input High Voltage
(Single-ended); NOTE 2
Input Low Voltage
(Single-ended); NOTE 2
Output Voltage Reference
Peak-to-Peak
Input Voltage
Input High Voltage Common
Mode Range; NOTE 3
Input
High
Current
Input
Low
Current
PCLK[0:1],
nPCLK[0:1],
CLK_SEL
PCLK[0:1],
CLK_SEL
nPCLK[0:1]
-10
-150
Min
-1.15
-1.835
-1.225
-1.87
-1.44
150
V
EE
+ 1.2
Typ
-0.94
-1.73
Max
-0.86
-1.63
-0.94
-1.535
-1.30
1000
V
CC
Min
-1.14
-1.875
-1.225
-1.87
-1.44
150
V
EE
+ 1.2
25°C
Typ
-0.96
-1.75
Max
-0.88
-1.665
- 0.94
-1.535
-1.30
1000
V
CC
Min
-1.13
-1.87
-1.225
-1.87
-1.44
150
V
EE
+ 1.2
85°C
Typ
-0.97
-1.765
Max
-0.89
-1.67
- 0.94
-1.535
-1.30
1000
V
CC
Units
V
V
V
V
V
mV
V
I
IH
150
150
150
µA
-10
-150
-10
-150
µA
µA
I
IL
For NOTES, see Table 3C above.
ICS853S310CVI
REVISION A NOVEMBER 17, 2010
4
©2010 Integrated Device Technology, Inc.
ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics,
V
CC
= V
CCO
= 3.0V to 3.8V, V
EE
= 0V; or V
EE
= -3.8V to -3.0V, V
CC
= V
CCO
= 0V;
T
A
= -40°C to 85°C
-40°C
Symbol
f
OUT
t
PD
tsk(o)
tsk(pp)
tjit
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output
Rise/Fall Time
20% to 80%
90
375
90
550
750
20
Min
Typ
Max
2
975
40
275
0.14
600
825
20
Min
25°C
Typ
Max
2
1050
40
275
625
885
20
Min
85°C
Typ
Max
2
1150
40
320
Units
GHz
ps
ps
ps
ps
t
R
/ t
F
375
80
400
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at f
OUT
≤
1.2GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS853S310CVI
REVISION A NOVEMBER 17, 2010
5
©2010 Integrated Device Technology, Inc.
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