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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 9FGU0631CKLFT
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9FGU0631CKLFT

Description
VFQFPN-40, Reel
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size361KB，16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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VFQFPN-40, Reel

9FGU0631CKLFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instructionHVQCCN,
Contacts40
Manufacturer packaging codeNDG40P2
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionVQFP-N 5MM X 5MM X. .9MM -NO LEA
JESD-30 codeS-XQCC-N40
JESD-609 codee3
length5 mm
Humidity sensitivity level3
Number of terminals40
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency25 MHz
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
Master clock/crystal nominal frequency27 MHz
Maximum seat height1 mm
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.4 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width5 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC

9FGU0631CKLFT Preview

6-O/P 1.5V PCIe Gen 1-2-3 Clock Generator
9FGU0631
DATASHEET
Description
The 9FGU0631 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 6 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Features/Benefits
•
LP-HCSL outputs; save 12 resistors compared to standard
•
•
PCIe devices
45mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 40-pin 5x5 mm VFQFPN; minimal board
space
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
•
•
•
•
•
Output Features
•
6 - 100MHz Low-Power (LP) HCSL DIF pairs
•
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
•
•
•
•
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <60ps
DIF phase jitter is PCIe Gen2 and Gen3 compliant
REF phase jitter is < 3.0ps RMS
•
•
•
•
•
Block Diagram
XIN/CLKIN_25
X2
vOE(5:0)#
DIF5
SS Capable PLL
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
DIF4
DIF3
DIF2
CONTROL
LOGIC
DIF1
DIF0
OSC
REF1.5
9FGU0631 OCTOBER 18, 2016
1
©2016 Integrated Device Technology, Inc.
9FGU0631 DATASHEET
Pin Configuration
^CKPWRGD_PD#
40 39 38 37 36 35 34 33 32 31
vSS_EN_tri
XIN/CLKIN_25
X2
VDDXTAL1.5
VDDREF1.5
vSADR/REF1.5
NC
GNDDIG
SCLK_3.3
SDATA_3.3
1
2
3
4
5
6
7
8
9
10
VDDDIG1.5
VDDIO
30
29
28
27
26
25
24
23
22
21
DIF1#
NC
vOE3#
DIF3#
DIF3
VDDIO
VDDA1.5
NC
vOE2#
DIF2#
DIF2
vOE1#
9FGU0631
Paddle is GND
11 12 13 14 15 16 17 18 19 20
VDD1.5
vOE0#
DIF0
DIF0#
VDDIO
DIF1
40-pin VFQFPN, 5x5 mm, 0.4mm pitch
v
^
prefix indicates internal 120KOhm pull down resistor
prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+
Read/Write Bit
x
x
Power Management Table
SMBus
DIFx
REF
OEx#
True O/P
Comp. O/P
OE bit
0
X
X
Low
Low
Hi-Z
1
1
1
0
Running
Running
Running
1
0
1
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
CKPWRGD_PD#
Power Connections
Pin Number
VDD
4
5
11
12,17,27,32,39
26
VDDIO
GND
41
41
8
41
41
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
6-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
2
VDD1.5
VDDIO
VDDIO
vOE5#
vOE4#
DIF5#
DIF4#
DIF5
DIF4
OCTOBER 18, 2016
9FGU0631 DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PIN NAME
vSS_EN_tri
XIN/CLKIN_25
X2
VDDXTAL1.5
VDDREF1.5
vSADR/REF1.5
NC
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.5
VDDIO
vOE0#
DIF0
DIF0#
VDD1.5
VDDIO
DIF1
DIF1#
NC
vOE1#
DIF2
DIF2#
vOE2#
NC
VDDA1.5
VDDIO
DIF3
DIF3#
vOE3#
VDD1.5
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
ePAD
PIN TYPE
LATCHED
IN
IN
OUT
PWR
PWR
LATCHED
I/O
N/A
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
PWR
PWR
OUT
OUT
N/A
IN
OUT
OUT
IN
N/A
PWR
PWR
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
GND
DESCRIPTION
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
Power supply for XTAL, nominal 1.5V
VDD for REF output. nominal 1.5V.
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
No Connection.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.5V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominally 1.5V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
No Connection.
1.5V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominally 1.5V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
Connect paddle to ground.
OCTOBER 18, 2016
3
6-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGU0631 DATASHEET
Test Loads
Low-Power Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
2pF
Rs
Alternate Differential Output Terminations
Rs
Zo
Units
33
100
Ohms
27
85
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
Driving LVDS
3.3 Volts
R7a
Cc
R7b
Rs
Rs
Cc
L4
R8a
R8b
LVDS CLK
Input
Driving LVDS inputs
Value
Receiver has Receiver does not
termination
have termination Note
10K ohm
140 ohm
5.6K ohm
75 ohm
0.1 uF
0.1 uF
1.2 volts
1.2 volts
Component
R7a, R7b
R8a, R8b
Cc
Vcm
6-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
4
OCTOBER 18, 2016
9FGU0631 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGU0631. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDxx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to all VDD pins
SMBus clock and data pins
MIN
-0.5
-0.5
-65
TYP
MAX
2
V
DD
+0.5V
3.3V
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1,3
1
1
1
1
Human Body Model
2000
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Current Consumption
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
I
DDAOP
Operating Supply Current
I
DDOP
I
DDIOOP
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
1
2
CONDITIONS
VDDA, All outputs active @100MHz
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
VDDIO, All outputs active @100MHz
VDDA, DIF outputs off, REF output running
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
VDDIO, DIF outputs off, REF output running
VDDA, all outputs off
All VDD, except VDDA and VDDIO, all outputs off
VDDIO, all outputs off
MIN
TYP
6.0
8.8
21
0.4
4.7
0.04
0.4
0.4
0.0003
MAX UNITS NOTES
9
14
30
1
7.5
0.1
1
1
0.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
2
2
2
I
DDAPD
I
DDPD
I
DDIOPD
I
DDAPD
I
DDPD
I
DDIOPD
Guaranteed by design and characterization, not 100% tested in production.
This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Duty Cycle
Skew, Output to Output
Jitter, Cycle to cycle
1
2
SYMBOL
t
DC
t
sk3
t
jcyc-cyc
CONDITIONS
Measured differentially, PLL Mode
Averaging on, V
T
= 50%
MIN
45
TYP
50
32
16
MAX UNITS NOTES
55
60
50
%
ps
ps
1,2
1
1,2
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
OCTOBER 18, 2016
5
6-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

9FGU0631CKLFT Related Products

9FGU0631CKLFT 9FGU0631CKILFT 9FGU0631CKLF
Description VFQFPN-40, Reel VFQFPN-40, Reel VFQFPN-40, Tray
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code VFQFPN VFQFPN VFQFPN
package instruction HVQCCN, HVQCCN, HVQCCN,
Contacts 40 40 40
Manufacturer packaging code NDG40P2 NDG40P2 NDG40P2
Reach Compliance Code compliant compliant compliant
ECCN code EAR99 EAR99 EAR99
Samacsys Description VQFP-N 5MM X 5MM X. .9MM -NO LEA VQFP-N 5MM X 5MM X. .9MM -NO LEA VQFP-N 5MM X 5MM X. .9MM -NO LEA
JESD-30 code S-XQCC-N40 S-XQCC-N40 S-XQCC-N40
JESD-609 code e3 e3 e3
length 5 mm 5 mm 5 mm
Humidity sensitivity level 3 3 3
Number of terminals 40 40 40
Maximum operating temperature 70 °C 85 °C 70 °C
Maximum output clock frequency 25 MHz 25 MHz 25 MHz
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code HVQCCN HVQCCN HVQCCN
Package shape SQUARE SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 260
Master clock/crystal nominal frequency 27 MHz 27 MHz 27 MHz
Maximum seat height 1 mm 1 mm 1 mm
Maximum supply voltage 1.575 V 1.575 V 1.575 V
Minimum supply voltage 1.425 V 1.425 V 1.425 V
Nominal supply voltage 1.5 V 1.5 V 1.5 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level COMMERCIAL INDUSTRIAL COMMERCIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal form NO LEAD NO LEAD NO LEAD
Terminal pitch 0.4 mm 0.4 mm 0.4 mm
Terminal location QUAD QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 5 mm 5 mm 5 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC

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