K4H510838J-BPB30 datasheet, PDF

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K4H510838J-BPB30: DescriptionDDR DRAM, 64MX8, 0.7ns, CMOS, PBGA60, HALOGEN FREE AND ROHS COMPLIANT, FBGA-60; Categorystorage storage; File Size674KB，27 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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K4H510838J-BPB30 Overview

DDR DRAM, 64MX8, 0.7ns, CMOS, PBGA60, HALOGEN FREE AND ROHS COMPLIANT, FBGA-60

K4H510838J-BPB30 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TBGA, BGA60,9X12,40/32
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
length	12 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	60
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA60,9X12,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.005 A
Maximum slew rate	0.18 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	9 mm

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Rev. 1.1, Feb. 2011

K4H510438J

K4H510838J

K4H511638J

512Mb J-die DDR SDRAM

60FBGA & 66TSOP-(II) with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

-1-

K4H510438J

K4H510838J

K4H511638J

datasheet

Rev. 1.1

DDR SDRAM

Table Of Contents

512Mb J-die DDR SDRAM

1. Key Features................................................................................................................................................................. 4

2. Ordering Information ..................................................................................................................................................... 4

3. Operating Frequencies ................................................................................................................................................. 4

4. Pin / Ball Description ..................................................................................................................................................... 5

4.1 Pin Description ........................................................................................................................................................ 5

4.2 Package Physical Dimension (TSOP II) .................................................................................................................. 6

4.3 Ball Description........................................................................................................................................................ 7

4.4 Package Physical Dimension (FBGA) ..................................................................................................................... 8

5. Block Diagram (32Mb x4 / 16Mb x8 / 8Mb x 16 I/O x4 Banks) ..................................................................................... 9

6. Input/Output Function Description ................................................................................................................................ 10

7. Command Truth Table .................................................................................................................................................. 11

8. General Description ...................................................................................................................................................... 12

9. Absolute Maximum Rating ............................................................................................................................................ 12

10. DC Operating Conditions ............................................................................................................................................ 12

11. DDR SDRAM Spec Items & Test Conditions .............................................................................................................. 13

12. Input/Output Capacitance ........................................................................................................................................... 13

13. Detailed test condition for DDR SDRAM IDD1 & IDD7A ............................................................................................ 14

14. DDR SDRAM IDD Spec Table .................................................................................................................................... 15

14.1 TSOP II.................................................................................................................................................................. 15

14.2 FBGA..................................................................................................................................................................... 16

15. AC Operating Conditions ............................................................................................................................................ 17

16. AC Overshoot/Undershoot specification for Address and Control Pins ...................................................................... 17

17. Overshoot/Undershoot specification for Data, Strobe and Mask Pins ........................................................................ 18

18. AC Timing Parameters & Specifications ..................................................................................................................... 19

19. System Characteristics for DDR SDRAM ................................................................................................................... 20

20. Component Notes ....................................................................................................................................................... 21

21. System Notes.............................................................................................................................................................. 23

22. IBIS : I/V Characteristics for Input and Output Buffers................................................................................................ 24

-3-

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