INTEGRATED CIRCUITS
XA-G3
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
Product specification
Supersedes data of 1998 Jun 04
IC25 Data Handbook
1998 Aug 14
Philips
Semiconductors
Philips Semiconductors
Product specification
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
XA-G3
FAMILY DESCRIPTION
The Philips Semiconductors XA (eXtended Architecture) family of
16-bit single-chip microcontrollers is powerful enough to easily
handle the requirements of high performance embedded
applications, yet inexpensive enough to compete in the market for
high-volume, low-cost applications.
The XA family provides an upward compatibility path for 80C51
users who need higher performance and 64k or more of program
memory. Existing 80C51 code can also easily be translated to run
on XA microcontrollers.
The performance of the XA architecture supports the
comprehensive bit-oriented operations of the 80C51 while
incorporating support for multi-tasking operating systems and
high-level languages such as C. The speed of the XA architecture,
at 10 to 100 times that of the 80C51, gives designers an easy path
to truly high performance embedded control.
The XA architecture supports:
•
Instruction set tailored for high level language support
•
Multi-tasking and real-time executives that include up to 32
vectored interrupts, 16 software traps, segmented data memory,
and banked registers to support context switching
•
Low power operation, which is intrinsic to the XA architecture,
includes power-down and idle modes.
More detailed information on the core is available in the XA User
Guide.
SPECIFIC FEATURES OF THE XA-G3
•
20-bit address range, 1 megabyte each program and data space.
(Note that the XA architecture supports up to 24 bit addresses.)
•
Upward compatibility with the 80C51 architecture
•
16-bit fully static CPU with a 24-bit program and data address
range
•
2.7V to 5.5V operation (EPROM and OTP are 5V
±
5%)
•
32K bytes on-chip EPROM/ROM program memory =
XA-G37/XA-G33
•
Eight 16-bit CPU registers each capable of performing all
arithmetic and logic operations as well as acting as memory
pointers. Operations may also be performed directly to memory.
•
512 bytes of on-chip data RAM
•
Three counter/timers with enhanced features
(equivalent to 80C51 T0, T1, and T2)
•
Both 8-bit and 16-bit CPU registers, each capable of performing
all arithmetic and logic operations.
•
An enhanced instruction set that includes bit intensive logic
operations and fast signed or unsigned 16
×
16 multiply and
32 / 16 divide
•
Watchdog timer
•
Two enhanced UARTs
•
Four 8-bit I/O ports with 4 programmable output configurations
•
44-pin PLCC and 44-pin LQFP packages
ORDERING INFORMATION
ROMless
P51XAG30JB BD
P51XAG30JB A
P51XAG30JF BD
P51XAG30JF A
P51XAG30KB BD
P51XAG30KB A
P51XAG30KF BD
P51XAG30KF A
ROM
P51XAG33JB BD
P51XAG33JB A
P51XAG33JF BD
P51XAG33JF A
P51XAG33KB BD
P51XAG33KB A
P51XAG33KF BD
P51XAG33KF A
EPROM
1
P51XAG37JB BD
P51XAG37JB A
P51XAG37JF BD
P51XAG37JF A
P51XAG37KB BD
P51XAG37KB A
P51XAG37KF BD
P51XAG37KF A
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
TEMPERATURE RANGE
°C
AND PACKAGE
0 to +70, Plastic Low Profile Quad Flat Pkg.
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Low Profile Quad Flat Pkg.
–40 to +85, Plastic Leaded Chip Carrier
0 to +70, Plastic Low Profile Quad Flat Pkg.
0 to +70, Plastic Leaded Chip Carrier
–40 to +85, Plastic Low Profile Quad Flat Pkg.
–40 to +85, Plastic Leaded Chip Carrier
FREQ
(MHz)
25
25
25
25
30
30
30
30
DRAWING
NUMBER
SOT389–1
SOT187–2
SOT389–1
SOT187–2
SOT389–1
SOT187–2
SOT389–1
SOT187–2
NOTE:
1. OTP = One Time Programmable EPROM. UV = Erasable EPROM.
1998 Aug 14
2
853-2052 19875
Philips Semiconductors
Product specification
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
XA-G3
PIN CONFIGURATIONS
44-Pin PLCC Package
6
1
40
44-Pin LQFP Package
44
34
7
39
1
PLCC
33
LQFP
17
29
11
23
18
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
V
SS
P1.0/A0/WRH
P1.1/A1
P1.2/A2
P1.3/A3
P1.4/RxD1
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
P3.6/WRL
P3.7/RD
XTAL2
XTAL1
V
SS
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
28
Function
V
DD
P2.0/A12D8
P2.1/A13D9
P2.2/A14D10
P2.3/A15D11
P2.4/A16D12
P2.5/A17D13
P2.6/A18D14
P2.7/A19D15
PSEN
ALE/PROG
NC
EA/V
PP
/WAIT
P0.7/A11D7
P0.6/A10D6
P0.5/A9D5
P0.4/A8D4
P0.3/A7D3
P0.2/A6D2
P0.1/A5D1
P0.0/A4D0
V
DD
SU00525
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
P3.6/WRL
P3.7/RD
XTAL2
XTAL1
V
SS
V
DD
P2.0/A12D8
P2.1/A13D9
P2.2/A14D10
P2.3/A15D11
P2.4/A16/D12
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
22
Function
P2.5/A17D13
P2.6/A18D14
P2.7/A19D15
PSEN
ALE/PROG
NC
EA/V
PP
/WAIT
P0.7/A11D7
P0.6/A10D6
P0.5/A9D5
P0.4/A8D4
P0.3/A7D3
P0.2/A6D2
P0.1/A5D1
P0.0/A4D0
V
DD
V
SS
P1.0/A0/WRH
P1.1/A1
P1.2/A2
P1.3/A3
P1.4/RxD1
SU00580
LOGIC SYMBOL
V
DD
V
SS
XTAL1
T2EX*
T2*
T
X
D1
R
X
D1
A3
A2
A1
A0/WRH
ADDRESS
BUS
XTAL2
RST
EA/WAIT
PSEN
ADDRESS AND DATA BUS
ALE
PORT 2
PORT 0
ALTERNATE FUNCTIONS
RxD0
TxD0
INT0
INT1
T0
T1/BUSW
WRL
RD
*
NOT AVAILABLE ON 40-PIN DIP PACKAGE
PORT 3
PORT 1
SU00526
1998 Aug 14
3
Philips Semiconductors
Product specification
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
XA-G3
BLOCK DIAGRAM
XA CPU Core
Program
Memory
Bus
32K BYTES
ROM/EPROM
SFR BUS
UART0
512 BYTES
STATIC RAM
Data Bus
UART1
PORT 0
TIMER 0 &
TIMER 1
PORT 1
TIMER 2
PORT 2
WATCHDOG
TIMER
PORT 3
SU00527
1998 Aug 14
4
Philips Semiconductors
Product specification
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
XA-G3
PIN DESCRIPTIONS
PIN. NO.
MNEMONIC
PLCC
V
SS
V
DD
P0.0 – P0.7
1, 22
23, 44
43–36
LQFP
16
17
37–30
I
I
I/O
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power down operation.
Port 0:
Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction
byte and address lines 4 through 11.
Port 0 also outputs the code bytes during program verification and receives code bytes during
EPROM programming.
P1.0 – P1.7
2–9
40–44,
1–3
I/O
Port 1:
Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 1 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
Port 1 also provides special functions as described below.
A0/WRH:
Address bit 0 of the external address bus when the external data bus is
configured for an 8 bit width. When the external data bus is configured for a 16
bit width, this pin becomes the high byte write strobe.
A1:
A2:
A3:
RxD1 (P1.4):
TxD1 (P1.5):
T2 (P1.6):
T2EX (P1.7):
Address bit 1 of the external address bus.
Address bit 2 of the external address bus.
Address bit 3 of the external address bus.
Receiver input for serial port 1.
Transmitter output for serial port 1.
Timer/counter 2 external count input/clockout.
Timer/counter 2 reload/capture/direction control
TYPE
NAME AND FUNCTION
2
40
O
3
4
5
6
7
8
9
P2.0 – P2.7
24–31
41
42
43
44
1
2
3
18–25
O
O
O
I
O
I/O
I
I/O
Port 2:
Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high
data/instruction byte and address lines 12 through 19. When the external program/data bus is used in
8-bit mode, the number of address lines that appear on port 2 is user programmable.
Port 2 also receives the low-order address byte during program memory verification.
P3.0 – P3.7
11,
13–19
5,
7–13
I/O
Port 3:
Port 3 is an 8-bit I/O port with a user configurable output type. Port 3 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. the operation of
port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
Port 3 pins receive the high order address bits during EPROM programming and verification.
Port 3 also provides various special functions as described below.
11
13
14
15
16
17
5
7
8
9
10
11
I
O
I
I
I/O
I/O
RxD0 (P3.0):
TxD0 (P3.1):
INT0 (P3.2):
INT1 (P3.3):
T0 (P3.4):
T1/BUSW (P3.5):
Receiver input for serial port 0.
Transmitter output for serial port 0.
External interrupt 0 input.
External interrupt 1 input.
Timer 0 external input, or timer 0 overflow output.
Timer 1 external input, or timer 1 overflow output. The value on this pin is
latched as the external reset input is released and defines the default
external data bus width (BUSW). 0 = 8-bit bus and 1 = 16-bit bus.
External data memory low byte write strobe.
External data memory read strobe.
18
19
12
13
O
O
WRL (P3.6):
RD (P3.7):
1998 Aug 14
5
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