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LF
PA
K
PSMN2R5-30YL
N-channel 30 V 2.4 mΩ logic level MOSFET in LFPAK
Rev. 04 — 10 March 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
drain-source on-state
resistance
gate-drain charge
total gate charge
V
GS
= 10 V; I
D
= 15 A;
T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 10 A;
V
DS
= 12 V; see
Figure 14;
see
Figure 15
V
GS
= 10 V; T
j(init)
= 25 °C;
I
D
= 100 A; V
sup
≤
30 V;
R
GS
= 50
Ω;
unclamped
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1
T
mb
= 25 °C; see
Figure 2
[1]
Min
-
-
-
-55
-
Typ
-
-
-
-
Max Unit
30
100
88
175
V
A
W
°C
mΩ
Static characteristics
1.79 2.4
Dynamic characteristics
Q
GD
Q
G(tot)
-
-
6.5
27
-
-
nC
nC
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source
avalanche energy
-
-
103
mJ
[1]
Continuous current is limited by package.
NXP Semiconductors
PSMN2R5-30YL
N-channel 30 V 2.4 mΩ logic level MOSFET in LFPAK
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN2R5-30YL
LFPAK
Description
Version
plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DSM
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
peak drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 100 A;
V
sup
≤
30 V; R
GS
= 50
Ω;
unclamped
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
t
p
≤
25 ns; f
≤
500 kHz;
E
DS(AL)
≤
240 nJ; pulsed
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
pulsed; t
p
≤
10 µs; T
mb
= 25 °C;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
[1]
Min
-
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
30
35
30
20
100
100
580
88
175
175
100
580
103
Unit
V
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
[1]
Continuous current is limited by package.
PSMN2R5-30YL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 04 — 10 March 2011
2 of 14
NXP Semiconductors
PSMN2R5-30YL
N-channel 30 V 2.4 mΩ logic level MOSFET in LFPAK
120
I
D
(A)
100
(1)
003aac656
120
P
der
(%)
80
03aa16
80
60
40
40
20
0
0
50
100
150
200
T
mb
(°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aac659
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
10
μs
100
μs
10
DC
1 ms
10 ms
100 ms
1
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN2R5-30YL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 04 — 10 March 2011
3 of 14
NXP Semiconductors
PSMN2R5-30YL
N-channel 30 V 2.4 mΩ logic level MOSFET in LFPAK
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance from
junction to mounting base
Conditions
see
Figure 4
Min
-
Typ
-
Max
1.4
Unit
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
-1
003aac657
0.1
0.05
0.02
P
δ
=
t
p
T
10
-2
single shot
t
p
t
T
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN2R5-30YL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 04 — 10 March 2011
4 of 14
ADI Reference Circuit
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