Temperature range as follows: A Version: −40°C to +85°C.
See the Terminology section.
3
Guaranteed by design.
4
Sample tested @ 25°C to ensure compliance.
5
See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, unless otherwise noted; V
CC
= 2.7 V to 3.6 V, V
REF
= 2.5 V.
Table 2. Timing Specifications
1
Parameter
f
DCLK2
t
ACQ
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
93
t
10
t
11
t
124
Limit at T
MIN
, T
MAX
10
2
1.5
10
60
60
200
200
60
10
10
200
0
200
200
Unit
kHz min
MHz max
µs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
Description
Acquisition time
CS falling edge to First DCLK rising edge
CS falling edge to BUSY three-state disabled
CS falling edge to DOUT three-state disabled
DCLK high pulse width
DCLK low pulse width
DCLK falling edge to BUSY rising edge
Data setup time prior to DCLK rising edge
Data valid to DCLK hold time
Data access time after DCLK falling edge
CS rising edge to DCLK ignored
CS rising edge to BUSY high impedance
CS rising edge to DOUT high impedance
1
2
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and are timed from a voltage level of 1.6 V.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4
t
12
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
02144-B-002
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
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