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Touch Screen Digitizer
AD7843
FEATURES
4-wire touch screen interface
Specified throughput rate of 125 kSPS
Low power consumption:
1.37 mW max at 125 kSPS with V
CC
= 3.6 V
Single supply, V
CC
of 2.2 V to 5.25 V
Ratiometric conversion
High speed serial interface
Programmable 8-bit or 12-bit resolution
2 auxiliary analog inputs
Shutdown mode: 1 µA max
16-lead QSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
+V
CC
PENIRQ
AD7843
X+
X–
Y+
Y–
4-TO-1
I/P
MUX
IN3
IN4
V
REF
T/H
PEN
INTERRUPT
COMP
GND
CHARGE
REDISTRIBUTION
DAC
+V
CC
SAR + ADC
CONTROL LOGIC
APPLICATIONS
Personal digital assistants
Smart hand-held devices
Touch screen monitors
Point-of-sales terminals
Pagers
SPORT
02144-B-001
DIN
CS
DOUT
DCLK
BUSY
Figure 1.
GENERAL DESCRIPTION
The AD7843 is a 12-bit successive approximation ADC with a
synchronous serial interface and low on resistance switches for
driving touch screens. The part operates from a single 2.2 V to
5.25 V power supply and features throughput rates greater than
125 kSPS.
The external reference applied to the AD7843 can be varied
from 1 V to +V
CC
, while the analog input range is from 0 V to
V
REF.
The device includes a shutdown mode that reduces the
current consumption to less than 1 µA.
The AD7843 features on-board switches. This, coupled with low
power and high speed operation, make this device ideal for
battery-powered systems such as personal digital assistants with
resistive touch screens, and other portable equipment. The part
is available in a 16-lead 0.15" quarter size outline package
(QSOP) and a 16-lead thin shrink small outline package
(TSSOP).
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Ratiometric conversion mode available eliminating errors
due to on-board switch resistances.
Maximum current consumption of 380 µA while operating
at 125 kSPS.
Power-down options available.
Analog input range from 0 V to V
REF
.
Versatile serial I/O port.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7843
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Terminology ...................................................................................... 7
Typical Performance Characteristics ............................................. 8
Circuit Information ........................................................................ 11
ADC Transfer Function............................................................. 11
Typical Connection Diagram ................................................... 11
Analog Input ............................................................................... 12
Control Register ......................................................................... 14
Power vs. Throughput Rate....................................................... 15
Serial Interface ............................................................................ 16
Detailed Serial Interface Timing .............................................. 17
Pen Interrupt Request................................................................ 19
Grounding and Layout .............................................................. 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
3/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings ....................................... 5
Addition to the PD0 and PD1 Section......................................... 14
Additions to Ordering Guide........................................................ 20
3/03—Data Sheet Changed from Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 16
Rev. B | Page 2 of 20
AD7843
SPECIFICATIONS
V
CC
= 2.7 V to 3.6 V, V
REF
= 2.5 V, f
SCLK
= 2 MHz, T
A
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
DC ACCURACY
Resolution
No Missing Codes
Integral Nonlinearity
2
Offset Error
2
Offset Error Match
3
Gain Error
2
Gain Error Match
3
Power Supply Rejection
SWITCH DRIVERS
On-Resistance
2
Y+, X+
Y−, X−
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
V
REF
Input Voltage Range
DC Leakage Current
V
REF
Input Impedance
V
REF
Input Current
3
AD7843A
1
12
11
±2
±6
1
0.1
±4
1
0.1
70
Unit
Bits
Bits min
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB typ
dB typ
Test Conditions/Comments
V
CC
= 2.7 V
5
6
0 to V
REF
±0.1
37
1.0/+V
CC
±1
5
20
1
1
2.4
0.4
±1
10
V
CC
− 0.2
0.4
0.4
±10
10
Straight (Natural) Binary
12
3
125
Ω typ
Ω typ
V
µA typ
pF typ
V min/max
µA max
GΩ typ
µA max
µA typ
µA max
V min
V max
µA max
pF max
V min
V max
V max
µA max
pF max
CS = GND or +V
CC
8 µA typ
f
SAMPLE
= 12.5 kHz
CS = +V
CC
; 0.001 µA typ
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
PENIRQ Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
Footnotes on next page.
Typically 10 nA, V
IN
= 0 V or +V
CC
I
SOURCE
= 250 µA; V
CC
= 2.2 V to 5.25 V
I
SINK
= 250 µA
I
SINK
= 250 µA; 100 kW pull-up
DCLK Cycles max
DCLK Cycles min
kSPS max
Rev. B | Page 3 of 20
AD7843
Parameter
POWER REQUIREMENTS
V
CC
(Specified Performance)
I
CC5
Normal Mode (f
SAMPLE
= 125 kSPS)
Normal Mode (f
SAMPLE
= 12.5 kSPS)
Normal Mode (Static)
Shutdown Mode (Static)
Power Dissipation
5
Normal Mode (f
SAMPLE
= 125 kSPS)
Shutdown
AD7843A
1
2.7/3.6
380
170
150
1
1.368
3.6
Unit
V min/max
µA max
µA typ
µA typ
µA max
mW max
µW max
Test Conditions/Comments
Functional from 2.2 V to 5.25 V
Digital I/Ps = 0 V or V
CC
V
CC
= 3.6 V, 240 µA typ
V
CC
= 2.7 V, f
DCLK
= 200 kHz
V
CC
= 3.6 V
V
CC
= 3.6 V
V
CC
= 3.6 V
1
2
Temperature range as follows: A Version: −40°C to +85°C.
See the Terminology section.
3
Guaranteed by design.
4
Sample tested @ 25°C to ensure compliance.
5
See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, unless otherwise noted; V
CC
= 2.7 V to 3.6 V, V
REF
= 2.5 V.
Table 2. Timing Specifications
1
Parameter
f
DCLK2
t
ACQ
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
93
t
10
t
11
t
124
Limit at T
MIN
, T
MAX
10
2
1.5
10
60
60
200
200
60
10
10
200
0
200
200
Unit
kHz min
MHz max
µs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
Description
Acquisition time
CS falling edge to First DCLK rising edge
CS falling edge to BUSY three-state disabled
CS falling edge to DOUT three-state disabled
DCLK high pulse width
DCLK low pulse width
DCLK falling edge to BUSY rising edge
Data setup time prior to DCLK rising edge
Data valid to DCLK hold time
Data access time after DCLK falling edge
CS rising edge to DCLK ignored
CS rising edge to BUSY high impedance
CS rising edge to DOUT high impedance
1
2
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and are timed from a voltage level of 1.6 V.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4
t
12
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
02144-B-002
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. B | Page 4 of 20
PCB Design
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