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SMCP-672061EV-15

Description
FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28
Categorystorage    storage   
File Size116KB,17 Pages
ManufacturerTEMIC
Websitehttp://www.temic.de/
Download Datasheet Parametric View All

SMCP-672061EV-15 Overview

FIFO, 16KX9, 15ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28

SMCP-672061EV-15 Parametric

Parameter NameAttribute value
MakerTEMIC
package instruction0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28
Reach Compliance Codeunknown
Maximum access time15 ns
period time25 ns
JESD-30 codeR-CDIP-T28
memory density147456 bit
memory width9
Number of functions1
Number of terminals28
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize16KX9
ExportableNO
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal locationDUAL
M672061E
16 K

9 CMOS With Programmable Half Full Flag Parallel
FIFO Rad Tolerant
Description
The M672061E implements a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the TEMIC FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin reset the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Using an array of eight transistors (8 T) memory cell, the
M672061E combine an extremely low standby supply
current (typ = 0.1
µA)
with a fast access time at 15 ns
over the full temperature range. All versions offer battery
backup data retention capability with a typical power
consumption at less than 2
µW.
For military/space applications that demand superior
levels of performance and reliability the M672061E is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) ,ESA SCC 9000 or
QML.
Features
D
D
D
D
D
First-in first-out dual port memory
16384
×
9 organisation
Fast Flag and access times: 15, 30 ns
Wide temperature range : – 55
°C
to + 125
°C
Programmable Half Full Flag
D
D
D
D
D
D
D
D
D
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation : 2 V data retention
TTL compatible
Single 5 V
±
10 % power supply
High Performance SCMOS Technology
Rev. C – June 30, 1999
1

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