INTEGRATED CIRCUITS
PCK2002PL
140 MHz PCI-X clock buffer
Preliminary specification
2001 Apr 04
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
140 MHz PCI-X clock buffer
PCK2002PL
FEATURES
•
General purpose and PCI-X 1:4 clock buffer
•
8-pin TSSOP 3
×
4.4 mm package
•
Same form, fit, and function as CDCV304
•
See PCK2001 for 48-pin 1:18 buffer part
•
See PCK2001M for 28-pin 1:10 buffer part
•
See PCK2001R for 16-pin 1:6 buffer part
•
Operating frequency: 0 – 140 MHz
•
Part-to-part skew < 500 ps
•
Low output skew: <200 ps
•
3.3 V operation
•
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
PIN CONFIGURATION
PCK2002PL
BUF_IN
OE
BUF_OUT0
V
SS
1
2
3
4
8
7
6
5
BUF_OUT3
BUF_OUT2
V
DD
BUF_OUT1
TOP VIEW
SA00569
PIN DESCRIPTION
PIN
NUMBER
1
3, 5, 7, 8
I/O
TYPE
Input
Output
Input
Input
Input
SYMBOL
BUF_IN
BUF_OUT
(0–3)
V
DD
OE
V
SS
FUNCTION
Buffered clock input
Buffered clock outputs
3.3 V supply
Output Enable
Ground
DESCRIPTION
The PCK2002PL is a 1–4 fanout buffer used as a high-performance,
low skew, general purpose and PCI-X clock buffer. It distributes one
input clock (BUF_IN) signal to four output clocks (BUF_OUT
n
).
6
2
4
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
r
t
f
I
CC
PARAMETER
Propagation delay
BUF_IN to BUF_OUT
n
Rise time
Fall time
Total supply current
CONDITIONS
V
CC
= 3.3 V, C
L
= 25 pF
V
CC
= 3.3 V, C
L
= 25 pF, 0.2V
DD
to 0.6V
DD
V
CC
= 3.3 V, C
L
= 25 pF, 0.6V
DD
to 0.2V
DD
V
CC
= 3.6 V
TYPICAL
2.9
2.8
800
600
50
UNIT
ns
ps
ps
µA
ORDERING INFORMATION
PACKAGES
8-Pin Plastic TSSOP
TEMPERATURE RANGE
–40 to +85
°C
ORDER CODE
PCK2002PLDP
DRAWING NUMBER
SOT530-1
2001 Apr 04
2
Philips Semiconductors
Preliminary specification
140 MHz PCI-X clock buffer
PCK2002PL
FUNCTION TABLE
OE
L
H
H
BUF_IN
X
L
H
BUF_OUTn
L
L
H
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to V
SS
(V
SS
= 0 V).
LIMITS
SYMBOL
V
DD
I
IK
V
I
I
OK
V
O
I
O
T
stg
P
tot
PARAMETER
DC 3.3 V supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
Storage temperature range
Power dissipation per package
plastic medium-shrink SO (SSOP)
For temperature range: 0 to +70
°C
above +55
°C
derate linearly with 11.3 mW/K
V
I
< 0
Note 2
V
O
> V
DD
or V
O
< 0
Note 2
V
O
≥
0 to V
DD
CONDITION
MIN
–0.5
—
–0.5
—
–0.5
—
–65
—
MAX
+4.3
–50
V
DD
+ 0.5
±50
V
DD
+ 0.5
±50
+150
850
UNIT
V
mA
V
mA
V
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
C
L
V
I
V
O
T
amb
PARAMETER
DC 3.3V supply voltage
Capacitive load
DC input voltage range
DC output voltage range
Operating ambient temperature range in free air
CONDITIONS
LIMITS
MIN
3.0
20
0
0
–40
MAX
3.6
30
V
DD
V
DD
+85
UNIT
V
pF
V
V
°C
2001 Apr 04
3
Philips Semiconductors
Preliminary specification
140 MHz PCI-X clock buffer
PCK2002PL
DC CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
V
DD
V
IH
V
IL
V
OH
HIGH level input voltage
LOW level input voltage
(V)
—
—
I
OH
= –1 mA
I
OH
= –24 mA
I
OH
= –12 mA
I
OL
= 1 mA
I
OL
= 24 mA
I
OL
= 12 mA
V
OUT
= 1 V
V
OUT
= 1.65 V
V
OUT
= 2.0 V
V
OUT
= 1.65 V
V
I
= V
DD
or GND
V
I
= V
DD
or GND
TEST CONDITIONS
OTHER
—
—
—
—
—
—
—
—
—
—
—
—
—
I
O
= 0
T
amb
= –40 to +85
°C
MIN
2.0
V
SS
– 0.3
V
DD
– 0.2
2.0
2.4
—
—
—
–50
—
60
—
—
—
MAX
V
DD
+ 0.3
0.8
—
—
—
0.2
0.8
0.55
—
–150
—
150
±5
100
V
V
V
V
V
V
V
V
mA
mA
mA
mA
µA
µA
UNIT
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
Output HIGH voltage
3.0
3.0
3.0 to 3.6
V
OL
Output LOW voltage
3.0
3.0
3.0
I
O
OH
Output HIGH current
3.3
3.0
I
O
OL
±I
I
I
CC
Output LOW current
Input leakage current
Quiescent supply current
3.3
3.6
3.6
2001 Apr 04
4
Philips Semiconductors
Preliminary specification
140 MHz PCI-X clock buffer
PCK2002PL
AC CHARACTERISTICS
SYMBOL
T
H
T
L
T
H
T
L
T
R
T
F
T
PLH
T
PHL
T
SKW
T
DDSKW
PARAMETER
CLK HIGH time
CLK LOW time
CLK HIGH time
CLK LOW time
Output rise slew rate
Output fall slew rate
Buffer LH propagation delay
Buffer HL propagation delay
Bus CLK skew
Device to device skew
TEST CONDITIONS
NOTES
66 MHz
140 MHz
2
3
2
3
4
4
5
5
1
1
MIN
6.0
6.0
2.9
3.0
1.4
1.5
1.8
1.8
—
—
LIMITS
T
amb
= –40 to +85
°C
TYP
6
—
—
—
—
1.7
2.2
2.9
2.8
—
—
MAX
—
—
—
—
4.0
4.0
3.4
3.4
200
500
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ps
ps
UNIT
NOTES:
1. CLK skew is only valid for equal loading of all outputs.
2. T
H
is measured at 0.5 V
DD
as shown in Figure 2.
3. T
L
is measured at 0.35 V
DD
as shown in Figure 2.
4. T
R
and T
F
are measured as a transition through the threshold region 0.2 V
DD
to 0.6 V
DD
and 0.6 V
DD
to 0.2 V
DD
.
5. Input edge rate for these tests must be faster than 1 V/ns.
6. All typical values are at V
CC
= 3.3 V and T
amb
= 25
°C.
AC WAVEFORMS
V
M
= 50% V
DD
C
L
= 25 pF
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
DD
BUF_IN
INPUT
V
M
V
M
TEST CIRCUIT
V
DD
V
DD
V
I
PULSE
GENERATOR
D.U.T.
R
T
0.6 V
DD
V
O
140
Ω
t
PLH
0.6 V
DD
V
M
BUF_OUT
0.2 V
DD
T
R
t
PHL
C
L
140
Ω
V
M
0.2 V
DD
SW00813
T
F
Figure 3. Load circuitry for switching times
SW00811
Figure 1. Load circuitry for switching times.
t
p
t
h
0.5 V
DD
0.4 V
DD
0.35 V
DD
t
l
SW00812
Figure 2. Buffer Output clock
2001 Apr 04
5
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