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QL1P100-8PUN132M

Description
Field Programmable Gate Array, 640 CLBs, 100000 Gates, 200MHz, 640-Cell, CMOS, PBGA132, 8 X 8 MM, 0.5 MM PITCH, LEAD FREE, TFBGA-132
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,92 Pages
ManufacturerQuickLogic Corporation
Websitehttps://www.quicklogic.com
Environmental Compliance  
Download Datasheet Parametric View All

QL1P100-8PUN132M Overview

Field Programmable Gate Array, 640 CLBs, 100000 Gates, 200MHz, 640-Cell, CMOS, PBGA132, 8 X 8 MM, 0.5 MM PITCH, LEAD FREE, TFBGA-132

QL1P100-8PUN132M Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerQuickLogic Corporation
Parts packaging codeBGA
package instructionTFBGA, BGA132,14X14,20
Contacts132
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
maximum clock frequency200 MHz
JESD-30 codeS-PBGA-B132
JESD-609 codee1
length8 mm
Humidity sensitivity level3
Configurable number of logic blocks640
Equivalent number of gates100000
Number of entries77
Number of logical units640
Output times77
Number of terminals132
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize640 CLBS, 100000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA132,14X14,20
Package shapeSQUARE
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply1.8,3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch0.5 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width8 mm
QuickLogic PolarPro
®
Device Data Sheet — QL1P075,
QL1P100, QL1P200, and QL1P300
••••••
Combining Low Power, Performance, Density, and Embedded RAM
• Quadrant-based segmentable clock networks
Device Highlights
Low Power Programmable Logic
• As low as 2.2 µA
• 0.18 µm, six layer metal CMOS process
• 1.8 V core voltage, 1.8/2.5/3.3 V drive
capable I/Os
• Up to 55 kilobits of SRAM
• Up to 238 I/Os available
• Up to 300,000 system gates
• Nonvolatile, instant-on
• IEEE 1149.1 boundary scan testing compliant
20 quad clock networks per device
4 quad clock networks per quadrant
1 dedicated clock network per quadrant
• Two user Configurable Clock Managers (CCMs)
Very Low Power (VLP) Mode
• QuickLogic PolarPro has a special VLP pin
which can enable a low power sleep mode that
significantly reduces the overall power
consumption of the device by placing the device in
standby
• Enter VLP mode from normal operation in less
than 250 µs (typical)
• Exit from VLP mode to normal operation in less
than 250 µs (typical)
Embedded Dual-Port SRAM
• Up to twelve dual-port 4-kilobit high performance
SRAM blocks
• True dual-port capability
• Embedded synchronous/asynchronous FIFO
controller
• Configurable and cascadable aspect ratio
Security Links
There are several security links to disable JTAG
access to the device. Programming these optional
links completely disables access to the device from
the outside world and provides an extra level of
design security not possible in SRAM-based FPGAs.
Figure 1: QuickLogic PolarPro Block Diagram
DDR/GPIO
DDR/GPIO
DDR/GPIO
DDR/GPIO
Programmable I/O
• Bank programmable drive strength
GPIO
CCM
GPIO
• Bank programmable slew rate control
• Independent I/O banks capable of supporting
multiple I/O standards in one device
• Native support for DDR I/Os
• Bank programmable I/O standards: LVTTL,
LVCMOS, LVCMOS18, PCI, SSTL2, SSTL3 and
SSDL18
Embedded RAM Blocks
FIFO Controller
GPIO
Fabric
GPIO
GPIO
GPIO
• Multiple low skew clock networks
GPIO
Embedded RAM Blocks
GPIO
GPIO
GPIO
1 dedicated global clock network
4 programmable global clock networks
© 2009 QuickLogic Corporation
www.quicklogic.com
GPIO
Advanced Clock Network
FIFO Controller
GPIO
1
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