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KMM374S1723ATS-G8

Description
Synchronous DRAM Module, 16MX72, 6ns, CMOS
Categorystorage    storage   
File Size139KB,10 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
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KMM374S1723ATS-G8 Overview

Synchronous DRAM Module, 16MX72, 6ns, CMOS

KMM374S1723ATS-G8 Parametric

Parameter NameAttribute value
MakerSAMSUNG
package instruction,
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N168
memory density1207959552 bit
Memory IC TypeSYNCHRONOUS DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals168
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX72
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL

KMM374S1723ATS-G8 Preview

KMM374S1723ATS
Revision History
Revision 0.0 (June 7, 1999)
PC100 Unbuffered DIMM
• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
• Symbol Change Notice
I
IL
I
IL
I
OL
Before
Input leakage current (inputs)
Input leakage current (I/O pins)
Output open @ DC characteristic table
I
LI
Io
After
Input leakage current
Output open @ DC characteristic table
Test Condition in
DC CHARACTERISTIC Change Notice
Symbol
I
CC2P ,
I
CC3P
I
CC2N ,
I
CC3N
I
CC4
Before
CKE
V
IL
(max), t
CC
= 15ns
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
2 Banks activated
After
CKE
V
IL
(max), t
CC
= 10ns
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
4 Banks activated
Revision 0.1 (July 5, 1999)
• Added Notes @OPERATING AC PARAMETER
Notes : 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.1 July 1999
KMM374S1723ATS
KMM374S1723ATS SDRAM DIMM
PC100 Unbuffered DIMM
16Mx72 SDRAM DIMM with ECC based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM374S1723ATS is a 16M bit x 72 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung KMM374S1723ATS consists of nine CMOS 16M x 8 bit
with 4banks Synchronous DRAMs in TSOP-II 400mil package
and a 2K EEPROM in 8-pin TSSOP package on a 168-pin
glass-epoxy substrate. One 0.1uF and one 0.22 uF decoupling
capacitors are mounted on the printed circuit board in parallel for
each SDRAM.
The KMM374S1723ATS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
FEATURE
• Performance range
Part No.
KMM374S1723ATS-G8
KMM374S1723ATS-GH
KMM374S1723ATS-GL
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V
±
0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,375mil),
single sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE
DQM0
Pin
Front
Pin Front
DQ18
DQ19
V
DD
DQ20
NC
*V
REF
*CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
WP
**SDA
**SCL
V
DD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
DD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
*CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
*CLK1
*A12
V
SS
CKE0
*CS3
DQM6
DQM7
*A13
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
DD
DQ52
NC
*V
REF
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
*CLK3
NC
**SA0
**SA1
**SA2
V
DD
29 DQM1 57
58
CS0
30
31
DU
59
60
32
V
SS
61
33
A0
62
34
A2
35
A4
63
64
36
A6
65
37
A8
38 A10/AP 66
39
BA1
67
68
40
V
DD
69
41
V
DD
42 CLK0 70
43
V
SS
71
72
44
DU
73
45
CS2
46 DQM2 74
47 DQM3 75
76
48
DU
77
49
V
DD
78
50
NC
51
79
NC
80
52
CB2
81
53
CB3
82
54
V
SS
55 DQ16 83
56 DQ17 84
PIN NAMES
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0, CLK2
CKE0
CS0, CS2
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
*V
REF
SDA
SCL
SA0 ~ 2
WP
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Check bit (Data-in/data-out)
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Address in EEPROM
Write protection
Don′t use
No connection
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 July 1999
KMM374S1723ATS
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
PC100 Unbuffered DIMM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP pin is connected to V
SS
through 47KΩ Resistor.
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be write-protected.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
DQ0 ~ 63
CB0 ~ 7
WP
V
DD
/V
SS
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Check bit
Write protection
Power supply/ground
Rev. 0.1 July 1999
KMM374S1723ATS
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
PC100 Unbuffered DIMM
DQM
CS
U0
DQM4
DQM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM6
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U6
DQM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS2
DQM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U2
DQM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U7
DQM
CS
U3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U8
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U4
Serial PD
SCL
SDA
A0
A1
A2
WP
47KΩ
SA0 SA1 SA2
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
3.3pF
*1
CLK0/2
10Ω
A0 ~ An, BA0 & 1
RAS
CAS
WE
CKE0
10Ω
DQn
V
DD
Vss
U0/U3
U5/U7
U1/U4
U6/U8
U2
Every DQpin of SDRAM
CLK1/3
One 0.1uF and one 0.22 uF Cap.
To all SDRAMs
per each SDRAM
*1 : For 4 loads, CLK2 only.
10Ω
10pF
Rev. 0.1 July 1999
KMM374S1723ATS
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
PC100 Unbuffered DIMM
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
= 1.4V
±
200 mV)
Pin
Symbol
C
ADD
C
IN
C
CKE
C
CLK
C
CS
C
DQM
C
OUT1
C
OUT2
Min
28
28
28
18
18
8
9
9
Max
50
50
50
25
30
10
12
12
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Address (A0 ~ A11, BA0 ~ BA1)
RAS, CAS, WE
CKE (CKE0)
Clock (CLK0, CLK2)
CS (CS0, CS2)
DQM (DQM0 ~ DQM7)
DQ (DQ0 ~ DQ63)
CB (CB0 ~ CB7)
Rev. 0.1 July 1999

KMM374S1723ATS-G8 Related Products

KMM374S1723ATS-G8 KMM374S1723ATS-GH KMM374S1723ATS-GL
Description Synchronous DRAM Module, 16MX72, 6ns, CMOS Synchronous DRAM Module, 16MX72, 6ns, CMOS Synchronous DRAM Module, 16MX72, 6ns, CMOS
Maker SAMSUNG SAMSUNG SAMSUNG
Reach Compliance Code unknown unknown unknown
ECCN code EAR99 EAR99 EAR99
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 6 ns 6 ns 6 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 code R-XDMA-N168 R-XDMA-N168 R-XDMA-N168
memory density 1207959552 bit 1207959552 bit 1207959552 bit
Memory IC Type SYNCHRONOUS DRAM MODULE SYNCHRONOUS DRAM MODULE SYNCHRONOUS DRAM MODULE
memory width 72 72 72
Number of functions 1 1 1
Number of ports 1 1 1
Number of terminals 168 168 168
word count 16777216 words 16777216 words 16777216 words
character code 16000000 16000000 16000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C
organize 16MX72 16MX72 16MX72
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
Certification status Not Qualified Not Qualified Not Qualified
self refresh YES YES YES
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount NO NO NO
technology CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form NO LEAD NO LEAD NO LEAD
Terminal location DUAL DUAL DUAL
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