DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3737
5150-BIT CCD LINEAR IMAGE SENSOR
The
µ
PD3737 is a 5150-bit high sensitivity CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal.
The
µ
PD3737 has high speed CCD register, so it is suitable for high resolution scanners and facsimiles
which scan high definition document at high speed.
FEATURES
• Valid photocell
• Photocell's pitch
• High response sensitivity
• Peak response wavelength
• Resolution
• Power supply
• Drive clock level
• High speed scan
• Data rate
5150-bit
7
µ
m
Providing a response 4.3 times better than the existing equivalent NEC
product (
µ
PD3571) to the light from a daylight fluorescent lamp
550 nm (green)
16 dot/mm across the shorter side of an A3-size (297
×
420 mm) sheet,
24 dot/mm across the shorter side of an A4-size (210
×
297 mm) sheet
+12 V
CMOS output under 5V operation
252
µ
s/line
20 MHz
ORDERING INFORMATION
Part Number
Package
CCD LINEAR IMAGE SENSOR 22 PIN CERAMIC DIP (CERDIP) (400 mil)
Quality Grade
Standard
µ
PD3737D
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC-3352
(O. D. No. IC-8925)
Date Published July 1994 P
Printed in Japan
The mark
shows revised points.
©
1994
µ
PD3737
BLOCK DIAGRAM
V
OD
4
φ
1L
12
14
φ
1
φ
R
22
V
OUT
18
Optical black (OB) 18 bits, invalid photocell 2 bits,
valid photocell 5150 bits, invalid photocell 2 bits
13
φ
TG
10
φ
2
2
AGND
5
AGND
9
φ
2L
2
µ
PD3737
PIN CONFIGURATION (Top View)
CCD LINEAR IMAGE SENSOR 22 PIN CERAMIC DIP (CERDIP) (400 mil)
No connection
1
NC
φ
R
NC
22
Reset gate clock
Analog ground
2
AGND
21
No connection
No connection
3
NC
NC
20
No connection
Output unit drain voltage
4
V
OD
NC
19
No connection
Analog ground
5
AGND
V
OUT
18
Output
No connection
6
NC
NC
17
No connection
No connection
7
NC
NC
16
No connection
No connection
8
NC
NC
15
No connection
Last-stage shift register clock 2
9
φ
2L
φ
2
NC
φ
1
φ
TG
φ
1L
14
Shift register clock 1
Shift register clock 2
10
13
Transfer gate clock
No connection
11
12
Last-stage shift register clock 1
PHOTOELEMENT STRUCTURE DIAGRAM
5
µ
m
2
µ
m
7
µ
m
Channel stopper
Aluminum
electrode
3
µ
PD3737
ABSOLUTE MAXIMUM RATINGS (T
a
= +25
°C)
Parameter
Output unit drain voltage
Shift register clock voltage
Last-stage shift register clock voltage
Reset signal voltage
Transfer gate signal voltage
Operating ambient temperature
Storage temperature
Symbol
V
OD
V
φ
1,
φ
2
V
φ
1L,
V
φ
2L
V
φ
R
V
φ
TG
T
opt
T
stg
Ratings
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–25 to +55
–40 to +100
Unit
V
V
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
a
= –25 to + 55
°C)
Parameter
Output unit drain voltage
Shift register clock signal high level
Symbol
V
OD
V
φ
1H
, V
φ
2H
,
V
φ
1LH
, V
φ
2LH
V
φ
1L
, V
φ
2L
,
V
φ
1LL
, V
φ
2LL
V
φ
RBH
V
φ
RBL
V
φ
TGH
V
φ
TGL
f
φ
R
MIN.
11.4
4.5
TYP.
12.0
5.0
MAX.
12.6
5.5
Unit
V
V
Shift register clock signal low level
Reset signal
φ
R high level
Reset signal
φ
R low level
Transfer gate signal high level
Transfer gate signal low level
Data rate
–0.3
0
+0.5
V
4.5
–0.3
4.5
–0.3
0.5
5.0
0
V
φ
1H
0
1
5.5
+0.5
V
φ
1H
+0.5
20
V
V
V
V
MHz
Remark 1.
Input reset signal
φ
R to pin 22 via capacitor. Concerning the connection method refer to
APPLICATION
EXAMPLE.
2.
Operating conditions of reset signal
φ
R is not the condition at device pins but the conditions of the
signal which applied to capacitor.
3.
When V
φ
TGH
> V
φ
1H
, image lag increases.
4
µ
PD3737
ELECTRICAL CHARACTERISTICS
T
a
= +25
°C,
V
DD
= 12 V, f
φ
1
= 0.5 MHz, data rate = 1 MHz, storage time = 10 ms
light source: 3200 K halogen lamp + C500 (infrared cut filter), input clock = 5 V
P-P
Parameter
Saturation voltage
Saturation exposure
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
Response
Response peak wavelength
Image lag
Offset level
Input capacity of shift register clock
pin
Input capacity of last-stage shift
register clock pin
Input capacity of reset pin
Input capacity of transfer gate clock
pin
Output fall delay time
Register imbalance
Transfer efficiency
Dynamic range
Reset feed-through noise
Symbol
V
sat
SE
PRNU
ADS
DSNU
P
W
Z
O
R
F
Test Conditions
MIN.
1.0
TYP.
1.5
0.2
±5
1.0
MAX.
Unit
V
lx·s
Daylight color fluorescent lamp
V
OUT
= 500 mV
Light shielding
Light shielding
–3
±10
3.0
+6
%
mV
mV
mW
+3
–1
100
0.2
0.5
9
kΩ
V/lx·s
nm
Daylight color fluorescent lamp
6
7.5
550
IL
V
OS
C
φ
1
C
φ
2
C
φ
1L
C
φ
2L
C
φ
R
C
φ
TG
t
d
Note
RI
TTE
DR
RFSN
V
OUT
= 1 V
2.0
0.3
3.0
800
50
10
150
1
5.0
%
V
pF
pF
pF
pF
ns
Time from 90 % to 10 % of
φ
2L fall
is 5ns.
V
OUT
= 500 mV
V
OUT
= 500 mV, f
φ
R1
= 20 MHz
V
sat
/DSNU
Light shielding
92
25
0
98
500
250
500
4
%
%
times
mV
Note
t
d
is defined as a time from 10 % of
φ
2L to 10 % of V
OUT
, output after passing through two steps of emitter
follower in the application example.
5
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