MPC826XAVV datasheet, PDF - EEWORLD Datasheet

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MPC826XAVV: Description32-BIT, 200 MHz, RISC PROCESSOR, PBGA480; Categorysemiconductor The embedded processor and controller; File Size788KB，50 Pages; ManufacturerFREESCALE (NXP)

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MPC826XAVV Overview

32-BIT, 200 MHz, RISC PROCESSOR, PBGA480

MPC826XAVV Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	480
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	1.9 V
Minimum supply/operating voltage	1.7 V
Rated supply voltage	1.8 V
External data bus width	64
Line speed	200 MHz
Processing package description	37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
state	ACTIVE
packaging shape	SQUARE
Package Size	GRID ARRAY, LOW PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1.27 mm
terminal coating	TIN LEAD
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	COMMERCIAL
Address bus width	32
Number of digits	32
boundary scan	Yes
Maximum FCLK clock frequency	66.66 MHz
floating point unit	Yes
Integrated cache	Yes
Microprocessor type	RISC PROCESSOR

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Freescale Semiconductor

Technical Data

Document Number: MPC8260AEC

Rev. 2.0, 06/2009

MPC8260A

PowerQUICC™ II Integrated

Communications Processor

Hardware Specifications

This document contains detailed information on power

considerations, DC/AC electrical characteristics, and AC

timing specifications for .25μm (HiP4) devices in the

PowerQUICC II™ MPC8260 communications processor

family. These devices include the MPC8260, the MPC8255,

the MPC8264, the MPC8265, and the MPC8266.

Throughout this document, these devices are collectively

referred to as the MPC826xA.

Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical and Thermal Characteristics . . . . . . . . . . . . 7

Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 23

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 46

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 48

Document Revision History . . . . . . . . . . . . . . . . . . . 48

Features

•

— 32-bit address decodes with programmable bank size

— Three user programmable machines, general-purpose chip-select machine, and page-mode

pipeline SDRAM machine

— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)

— Dedicated interface logic for SDRAM

CPU core can be disabled and the device can be used in slave mode to an external core

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support

for communications protocols

— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols (only FCC1 and

FCC2 on the MPC8255):

– 10/100-Mbit Ethernet/IEEE Std. 802.3® CDMA/CS interface through media independent

interface (MII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,

AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external

connections

– Transparent

– HDLC—Up to T3 rates (clear channel)

— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split

into four subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM

interfaces up to four TDM interfaces per MCC

— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting

the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BISYNC) communications

– Transparent

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provide management for BRI devices as general circuit interface (GCI) controllers in time-

division-multiplexed (TDM) channels

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0

Freescale Semiconductor

MPC826XAVV Related Products

	MPC826XAVV	MPC826XACVV
Description	32-BIT, 200 MHz, RISC PROCESSOR, PBGA480	32-BIT, 200 MHz, RISC PROCESSOR, PBGA480
Number of functions	1	1
Number of terminals	480	480
Maximum operating temperature	70 Cel	70 Cel
Minimum operating temperature	0.0 Cel	0.0 Cel
Maximum supply/operating voltage	1.9 V	1.9 V
Minimum supply/operating voltage	1.7 V	1.7 V
Rated supply voltage	1.8 V	1.8 V
External data bus width	64	64
Line speed	200 MHz	200 MHz
Processing package description	37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480	37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
state	ACTIVE	ACTIVE
packaging shape	SQUARE	SQUARE
Package Size	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
surface mount	Yes	Yes
Terminal form	BALL	BALL
Terminal spacing	1.27 mm	1.27 mm
terminal coating	TIN LEAD	TIN LEAD
Terminal location	BOTTOM	BOTTOM
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY
Temperature level	COMMERCIAL	COMMERCIAL
Address bus width	32	32
Number of digits	32	32
boundary scan	Yes	Yes
Maximum FCLK clock frequency	66.66 MHz	66.66 MHz
floating point unit	Yes	Yes
Integrated cache	Yes	Yes
Microprocessor type	RISC PROCESSOR	RISC PROCESSOR

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