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MPC8360ECVVAJDHA

Description
32-BIT, 400 MHz, RISC PROCESSOR, PBGA740
Categorysemiconductor    The embedded processor and controller   
File Size638KB,102 Pages
ManufacturerFREESCALE (NXP)
Download Datasheet Parametric View All

MPC8360ECVVAJDHA Overview

32-BIT, 400 MHz, RISC PROCESSOR, PBGA740

MPC8360ECVVAJDHA Parametric

Parameter NameAttribute value
External data bus width32
Number of terminals740
Line speed400 MHz
Processing package description37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740
EU RoHS regulationsYes
stateActive
microprocessor_microcontroller_peripheral_ic_typeMICROPROCESSOR, RISC
Address bus width32
Number of digits32
boundary scanYES
clock_frequency_max66.67 MHz
formFLOATING POINT
Integrated cacheYES
jesd_30_codeS-PBGA-B740
jesd_609_codee2
low power modeYES
moisture_sensitivity_level3
Packaging MaterialsPLASTIC/EPOXY
ckage_codeLBGA
ckage_equivalence_codeBGA740,37X37,40
packaging shapeSQUARE
Package SizeGRID ARRAY, LOW PROFILE
eak_reflow_temperature__cel_260
wer_supplies1.8/2.5,3.3
qualification_statusCOMMERCIAL
seated_height_max1.69 mm
sub_categoryMicroprocessors
Rated supply voltage1.2 V
Minimum supply voltage1.14 V
Maximum supply voltage1.26 V
surface mountYES
CraftsmanshipCMOS
terminal coatingTIN COPPER/TIN SILVER
Terminal formBALL
Terminal spacing1 mm
Terminal locationBOTTOM
ime_peak_reflow_temperature_max__s_40
length37.5 mm
width37.5 mm
Freescale Semiconductor
Technical Data
Document Number: MPC8360EEC
Rev. 5, 09/2011
MPC8360E/MPC8358E
PowerQUICC II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications
This document provides an overview of the MPC8360E/58E
PowerQUICC II Pro processor revision 2.x TBGA features, including a
block diagram showing the major functional components. This device is
a cost-effective, highly integrated communications processor that
addresses the needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include next generation
DSLAMs, network interface cards for 3G base stations (Node Bs),
routers, media gateways, and high end IADs. The device extends current
PowerQUICC II Pro offerings, adding higher CPU performance,
additional functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related to
time-to-market, price, power, and package size. This device can be used
for the control plane and also has data plane functionality.
For functional characteristics of the processor, refer to the
MPC8360E
PowerQUICC II Pro Integrated Communications Processor Reference
Manual,
Rev. 3.
To locate any updates for this document, refer to the MPC8360E product
summary page on our website listed on the back cover of this document
or contact your Freescale sales office.
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1
Overview
This section describes a high-level overview including features and
general operation of the MPC8360E/58E PowerQUICC II Pro processor.
A major component of this device is the e300 core, which includes
32 Kbytes of instruction and data cache and is fully compatible with the
Power Architecture™ 603e instruction set. The new QUICC Engine
module provides termination, interworking, and switching between a
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . 12
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 14
RESET Initialization . . . . . . . . . . . . . . . . . . . . 16
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
UCC Ethernet Controller: Three-Speed Ethernet,
MII Management . . . . . . . . . . . . . . . . . . . . . . . 25
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Package and Pin Listings . . . . . . . . . . . . . . . . . 63
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
System Design Information . . . . . . . . . . . . . . . 96
Ordering Information . . . . . . . . . . . . . . . . . . . . 99
Document Revision History . . . . . . . . . . . . . 100
© 2011 Freescale Semiconductor, Inc. All rights reserved.
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