IS61(64)LF12832A IS64VF12832A
IS61(64)LF12836A IS61(64)VF12836A
IS61(64)LF25618A IS61(64)VF25618A
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
JANUARY 2010
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LF: V
DD
3.3V + 5%, V
DDQ
3.3V/2.5V + 5%
VF: V
DD
2.5V -5% +10%, V
DDQ
2.5V -5% +10%
• JEDEC 100-Pin TQFP, 119-pin PBGA, and
165-pin PBGA packages
• Automotive temperature available
• Lead-free available
IS64VF12832A,
IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are
high-speed, low-power synchronous static RAMs designed
to provide burstable, high-performance memory for commu-
nication and networking applications. The
IS61(64)LF12832A is organized as 131,072 words by 32
bits. The IS61(64)LF/VF12836A is organized as 131,072
words by 36 bits. The IS61(64)LF/VF25618A is organized
as 262,144 words by 18 bits. Fabricated with
ISSI
's
advanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All syn-
chronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
DESCRIPTION
The
ISSI
IS61(64)LF12832A,
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-6.5
6.5
7.5
133
-7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
1
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
119 BGA PACKAGE PIN CONFIGURATION
128K
X
36 (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
NC
3
A
A
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
BWd
Vss
Vss
Vss
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
A
NC
5
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
NC
6
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
BWx
(x=a-d)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
NC
DQa-DQd
DQPa-Pd
V
DD
V
DDQ
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
CE,
CE2,
CE2
Synchronous Chip Select
4
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
119 BGA PACKAGE PIN CONFIGURATION
256K
X
18 (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
A
CE2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
NC
3
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
NC
NC
5
A
A
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
NC
6
A
CE2
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE,
CE2,
CE2
BWx
(x=a,b)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
NC
DQa-DQb
DQPa-Pb
V
DD
V
DDQ
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc.
Rev. E
01/08/2010
5
Domestic Chip Exchange
京公网安备 11010802033920号
EEWORLD
