MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC74VHC4051/D
Advance Information
Demultiplexers
Analog Multiplexers/
MC74VHC4051
MC74VHC4052
MC74VHC4053
High–Performance Silicon–Gate CMOS
The MC74VHC4051, MC74VHC4052 and MC74VHC4053 utilize silicon–
gate CMOS technology to achieve fast propagation delays, low ON
resistances, and low OFF leakage currents. These analog multiplexers/
demultiplexers control analog voltages that may vary across the complete
power supply range (from VCC to VEE).
The VHC4051, VHC4052 and VHC4053 are identical in pinout to the
high–speed HC4051A, HC4052A and HC4053A, and the metal–gate
MC14051B, MC14052B and MC14053B. The Channel–Select inputs
determine which one of the Analog Inputs/Outputs is to be connected, by
means of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than R on of metal–gate CMOS analog
switches.
For a multiplexer/demultiplexer with channel–select latches, see
VHC4351.
•
Fast Switching and Propagation Speeds
•
Low Crosstalk Between Switches
•
Diode Protection on All Inputs/Outputs
•
Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V
•
Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
•
Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
•
Low Noise
•
In Compliance With the Requirements of JEDEC Standard No. 7A
•
Chip Complexity: VHC4051 — 184 FETs or 46 Equivalent Gates
VHC4052 — 168 FETs or 42 Equivalent Gates
VHC4053 — 156 FETs or 39 Equivalent Gates
LOGIC DIAGRAM
MC74VHC4051
Single–Pole, 8–Position Plus Common Off
X0
14
X1
15
X2
ANALOG
12
MULTIPLEXER/
INPUTS/ X3
1
DEMULTIPLEXER
OUTPUTS X4
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
13
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC74VHCXXXXD
MC74VHCXXXXDT
SOIC
TSSOP
FUNCTION TABLE – MC74VHC4051
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
C
L
L
L
L
H
H
H
H
X
Select
B
A
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
3
X
COMMON
OUTPUT/
INPUT
Pinout: MC74VHC4051
(Top View)
VCC
16
X2
15
X1
14
X0
13
X3
12
A
11
B
10
C
9
1
X4
2
X6
3
X
4
X7
5
X5
6
7
Enable VEE
8
GND
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
07/99
©
Motorola, Inc. 1999
1
REV 2
MC74VHC4051 MC74VHC4052 MC74VHC4053
FUNCTION TABLE – MC74VHC4052
LOGIC DIAGRAM
MC74VHC4052
Double–Pole, 4–Position Plus Common Off
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
1
5
2
4
10
9
6
12
Control Inputs
Select
Enable
L
L
L
L
H
X = Don’t Care
B
L
L
H
H
X
A
L
H
L
H
X
ON Channels
Y0
Y1
Y2
Y3
NONE
X0
X1
X2
X3
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y SWITCH
3
Y
Pinout: MC74VHC4052
(Top View)
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
VCC
16
X2
15
X1
14
X
13
X0
12
X3
11
A
10
B
9
CHANNEL-SELECT
INPUTS
ENABLE
1
Y0
2
Y2
3
Y
4
Y3
5
Y1
6
7
Enable VEE
8
GND
FUNCTION TABLE – MC74VHC4053
LOGIC DIAGRAM
MC74VHC4053
Triple Single–Pole, Double–Position Plus Common Off
X0
13
X1
Y0
1
Y1
Z0
3
Z1
A
10
CHANNEL-SELECT
B
INPUTS
9
C
6
ENABLE
11
5
2
12
14
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
Select
C
B
A
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
X1
X0
X1
X0
X1
X0
X1
X SWITCH
X
ANALOG
INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON
OUTPUTS/INPUTS
Z SWITCH
4
Z
X = Don’t Care
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
Pinout: MC74VHC4053
(Top View)
VCC
16
Y
15
X
14
X1
13
X0
12
A
11
B
10
C
9
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
1
Y1
2
Y0
3
Z1
4
Z
5
Z0
6
7
Enable VEE
8
GND
MOTOROLA
2
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
MC74VHC4051 MC74VHC4052 MC74VHC4053
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MAXIMUM RATINGS*
Symbol
VCC
VEE
VIS
Vin
I
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to VEE)
– 0.5 to + 7.0
– 0.5 to + 14.0
– 7.0 to + 5.0
VEE – 0.5 to
VCC + 0.5
±
25
500
450
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air,
Storage Temperature Range
– 0.5 to VCC + 0.5
mA
PD
SOIC Package†
TSSOP Package†
mW
Tstg
TL
– 65 to + 150
260
_
C
_
C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: – 6.1 mW/
_
C from 65
_
to 125
_
C
RECOMMENDED OPERATING CONDITIONS
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Symbol
VCC
VEE
VIS
Vin
Parameter
Min
2.0
2.0
Max
Unit
V
V
V
V
V
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to VEE)
6.0
12.0
Negative DC Supply Voltage, Output (Referenced to
GND)
Analog Input Voltage
– 6.0
VEE
GND
VCC
VCC
1.2
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
GND
VIO*
TA
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Channel Select or Enable Inputs)
– 55
0
0
0
0
+ 125
1000
800
500
400
_
C
ns
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
* For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
3
MOTOROLA
MC74VHC4051 MC74VHC4052 MC74VHC4053
DC CHARACTERISTICS — Digital Section
(Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol
S b l
VIH
Parameter
P
Minimum High–Level Input Voltage,
Channel–Select or Enable Inputs
Condition
C di i
Ron = Per Spec
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
6.0
Guaranteed Limit
–55 to 25°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
0.1
≤85°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
≤125°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
Unit
U i
V
VIL
Maximum Low–Level Input Voltage,
Channel–Select or Enable Inputs
Ron = Per Spec
V
Iin
ICC
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND,
VEE = – 6.0 V
Channel Select, Enable and
VIS = VCC or GND; VEE = GND
VIO = 0 V
VEE = – 6.0
µA
µA
6.0
6.0
1
4
10
40
40
160
DC ELECTRICAL CHARACTERISTICS
Analog Section
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Î
Guaranteed Limit
S b l
Symbol
Ron
P
Parameter
T
Test C di i
Conditions
VCC
V
3.0
4.5
4.5
6.0
3.0
4.5
4.5
6.0
3.0
4.5
4.5
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
VEE
V
– 55 to
25
_
C
TBD
190
120
100
TBD
150
100
80
TBD
30
12
10
0.1
0.2
0.1
0.1
0.2
0.1
0.1
v
85
_
C
v
125
_
C
TBD
240
150
125
TBD
190
125
100
TBD
35
15
12
0.5
2.0
1.0
1.0
2.0
1.0
1.0
TBD
280
170
140
TBD
230
140
115
TBD
40
18
14
1.0
4.0
2.0
2.0
4.0
2.0
2.0
U i
Unit
Ω
Maximum “ON” Resistance
Vin = VIL or VIH
VIS = VCC to VEE
IS
2.0 mA (Figures 1, 2)
v
0.0
0.0
– 4.5
– 6.0
0.0
0.0
– 4.5
– 6.0
0.0
0.0
– 4.5
– 6.0
Vin = VIL or VIH
VIS = VCC or VEE (Endpoints)
IS
2.0 mA (Figures 1, 2)
v
∆R
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIL or VIH
VIS = 1/2 (VCC – VEE)
IS
2.0 mA
Ω
v
Ioff
Maximum Off–Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIO = VCC – VEE;
Switch Off (Figure 3)
Vin = VIL or VIH;
VIO = VCC – VEE;
Switch Off (Figure 4)
µA
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
Maximum Off–Channel VHC4051
Leakage Current,
VHC4052
Common Channel
VHC4053
Ion
Maximum On–Channel VHC4051
Leakage Current,
VHC4052
Channel–to–Channel VHC4053
Vin = VIL or VIH;
Switch–to–Switch =
VCC – VEE; (Figure 5)
µA
MOTOROLA
4
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
MC74VHC4051 MC74VHC4052 MC74VHC4053
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
S b l
tPLH,
tPHL
Parameter
P
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25°C
370
TBD
74
63
60
TBD
12
10
290
TBD
58
49
345
TBD
69
59
10
35
130
80
50
1.0
≤85°C
465
TBD
93
79
75
TBD
15
13
364
TBD
73
62
435
TBD
87
74
10
35
130
80
50
1.0
≤125°C
550
TBD
110
94
90
TBD
18
15
430
TBD
86
73
515
TBD
103
87
10
35
130
80
50
1.0
Unit
U i
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
Cin
CI/O
Maximum Input Capacitance, Channel–Select or Enable Inputs
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I: VHC4051
VHC4052
VHC4053
Feedthrough
pF
pF
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation C
P
Di i i Capacitance (Fi
i
(Figure 13)*
VHC4051
VHC4052
VHC4053
45
80
45
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC .
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
5
MOTOROLA
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