IS61NW6432
IS61NW6432
64K x 32 SYNCHRONOUS STATIC RAM
WITH NO-WAIT STATE BUS FEATURE
FEATURES
Fast access time:
5 ns-100 MHz; 6 ns-83 MHz;
7 ns-75 MHz; 8ns-66 MHz;
No wait cycles between Read and write
Internal self-timed write cycle
Individual byte write Control
Clock controlled, registered address, data and
control
Pentium
TM
or Inear burst sequence control using
MODE input
Three chip enables for simple depth depth
expansion and adress pipelining
Common data inputs and data outputs
JEDEC 100-pin LQFP and PQFP package
Single+3.3V power supply
Optional data strobe pin (#80) for latching data
(See page 12 for detailed timing)
DESCRIPTION
The IS61NW6432 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
no-wait bus, secondary cache for the Pentium, 680X0, and
Power PC microprocessors. It is organized as 65,536 words
by 32 bits, fabricated with ICSI's advanced CMOS technology.
Incorporating a no-wait bus, wait cycles are eliminated when
the bus switches from read to write, or write to read. This
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit.
All synchronous inputs pass through registers controlled by a
Positive-edge-trggered clock input. Operations may be sus-
pended and all synchronous inputs ignored when Clock Enable,
CEN
is HIGH. In this state the internal device will hold their
previous values.
When the ADV/LD is HIGH the internal burst counter is
incremented. New external addresses can be loaded when
ADV/LD is LOW.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock inputs and when RD/WE is LOW.
Separate byte enables allow indiviual bytes to be written.
BW1
controls I/O1-I/P8;
BW2
controls I/O9-I/O16;BW3 controls I/
O17-I/O24;
BW4
controls I/O25-I/O32. All Bytes are written
when
BW1, BW2, BW3,
and
BW4
are LOW.
MODE pin upon power up is in interleave burst mode. It can be
connected to GND or Vcc
Q
to alter power up state.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SSR006-0B
1
IS61NW6432
TRUTH TABLE
(1)
Operation
Bein New Write Cycle
Begin New Read Cycle
Advance Burst Counter
(Burst Write)
Advance Burst Counter
(BurstRead)
Deselect (2 Cycle)
Hold/NOOP
"
X
X
X
X
H
X
L
X
L
H
X
X
L-H
L-H
Address
Used
External
External
Internal
Internal
/W
R/W
L
H
X
X
CEx
L
L
X
X
/LD
ADV/LD
L
L
H
H
CEN
L
L
L
L
BW
BWx
Valid
X
Valid
X
CLK
L-H
L-H
L-H
L-H
Notes:
1. "X" Means don't care.
2. When ADV/LD signal is sampled HI|GH, the internal burst counter is incremented. The R/W signal is ignored when the counter
is advanced, Therefore, the nature of the burst cycle (Read or Write) is deternined by the status of the R/W signal when the
first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when
CEx
is sampled HIGH and ADV/LD sampled LOW at rising edge of clock. The data bus will
tristate two cycles after deselect is initiated.
4. When
CEN
is sampled high at the rising edge of clock, that clock edge is blocked form propogating through the part. The state
of all the internal registers remains unchanged.
PARTIAL TRUTH TABLE(Non-burst)
Function
READ
WRITE Byte 1
WRITE Byte 2
WRITE Byte 3
WRITE Byte 4
WRITE All Bytes
GW
H
L
L
L
L
L
BW1
X
L
H
H
H
L
BW2 BW3
X
H
L
H
H
L
X
H
H
L
H
L
BW4
X
H
H
H
L
L
CEx
L
L
L
L
L
X
ADV/LD
/LD
L
L
L
L
L
L
FUNCTIONAL TIMING DIAGRAM
4
Integrated Circuit Solution Inc.
SSR006-0B
Electronics Design Contest
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