IDT71V33S55J datasheet, PDF - EEWORLD Datasheet

IDT71V33S55J: DescriptionDual-Port SRAM, 2KX16, 55ns, CMOS, PQCC68, PLASTIC, LCC-68; Categorystorage storage; File Size570KB，14 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V33S55J Overview

Dual-Port SRAM, 2KX16, 55ns, CMOS, PQCC68, PLASTIC, LCC-68

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	PLASTIC, LCC-68
Contacts	68
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	55 ns
I/O type	COMMON
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
length	24.2062 mm
memory density	32768 bit
Memory IC Type	DUAL-PORT SRAM
memory width	16
Humidity sensitivity level	1
Number of functions	1
Number of ports	2
Number of terminals	68
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2KX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.005 A
Minimum standby current	3 V
Maximum slew rate	0.185 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	24.2062 mm

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