Features
•
Industry-standard architecture
– Emulates Many 20-pin PALs
®
– Low-cost, easy to use software tools
High speed electrically-erasable programmable logic devices (EE PLD)
– 5ns maximum pin-to-pin delay
Low power, 100μA pin controlled power-down mode option
CMOS and TTL compatible inputs and outputs
– I/O pin keeper circuits
Advanced flash technology
– Reprogrammable
– 100% tested
High reliability CMOS process
– 20 year data retention
– 100 erase/write cycles
– 2,000V ESD protection
– 200mA latchup immunity
Commercial and industrial temperature ranges
Dual-in-line and surface mount packages in standard pinouts
PCI compliant
Green (ROHS compliant) package options available
•
•
•
•
•
High Performance
Electrically-erasable
Programmable
Logic Devices
Atmel ATF16V8C
•
•
•
•
Description
The Atmel
®
ATF16V8C is a high performance EECMOS programmable logic device (PLD)
that utilizes the Atmel proven electrically-erasable (EE) Flash memory technology. Offered
options include speeds down to 5ns and a 100μA pin-controlled power-down mode. All
speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges,
and 5V ± 5% for commercial range 5V devices.
The ATF16V8C incorporates a superset of the generic architectures, which allows direct
replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are
each allocated eight product terms. Three different modes of operation are configured auto-
matically with software, and allow highly complex logic functions to be realized.
The ATF16V8C can significantly reduce total system power, thereby enhancing system reli-
ability and reducing power supply costs. When pin 4 is configured as the power-down
control pin, supply current drops to less than 100μA whenever the pin is high. If the power-
down feature isn't required for a particular application, pin 4 may be used as a logic input.
Also, the pin-keeper circuits eliminate the need for internal pull-up resistors along with their
attendant power consumption.
0425H–PLD–3/11
Figure 0-1.
Block diagram
Note:
1. Includes optional PD control pin
Figure 0-2.
Pin name
CLK
I
I/O
OE
V
CC
PD
Pin configurations
Function
Clock
Logic inputs
Bidirectinoal buffers
Output enable
+5V supply
Power-down
TSSOP
Top view
DIP/SOIC
Top view
PLCC
Top view
2
Atmel ATF16V8C
0425H–PLD–3/11
I8
GND
I9/OE
I/O
I/O
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
3
2
1
20
19
9
10
11
12
13
I2
I1
I/CLK
VCC
I/O
PD/I3
I4
I5
I6
I7
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
Atmel ATF16V8C
1.
Absolute maximum ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
maximum ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
1. Minimum voltage is -0.6V DC, which may undershoot
to -2.0V for pulses of less than 20ns. Maximum out-
put pin voltage is V
CC
+ 0.75V DC, which may
overshoot to 7.0V for pulses of less than 20ns.
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Voltage on any pin with respect to ground . . . . . -2.0V to +7.0V
(1)
Voltage on input pins with respect to ground
during programming . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V
(1)
Programming voltage with
respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V
(1)
Note:
2.
DC and AC characteristics
DC and AC operating conditions
Commercial
Industrial
-40C - 85C
5V ± 10%
Table 2-1.
Operating temperature (Ambient)
V
CC
power supply
0C - 70C
5V ± 5%
Table 2-2.
Symbol
I
IL
I
IH
I
CC1
(1)
DC characteristics
Parameter
Input or I/O low leakage current
Input or I/O high leakage current
Power supply current, standby
Power supply current,
Power-down mode
Output short circuit current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
V
CC
= Min; All outputs
I
OL
= 24mA
V
CC
= Min
I
OL
= -4.0mA
Com.
V
CC
= Min
V
CC
= Min
Com., Ind.
2.4
24.0
12.0
-4.0
Condition
0
V
IN
V
IL
(Max)
3.5
V
IN
V
CC
15MHz, V
CC
= Max,
V
IN
= 0, V
CC
, outputs open
V
CC
= Max, V
IN
= 0, V
CC
V
OUT
= 0.5V;
V
CC
= 5V; T
A
= 25°C
Min < V
CC
< Max
-0.5
2.0
Com.
Ind.
Com.
Ind.
10
10
Min
Typ
Max
-10.0
10.0
115
130
100
105
-150
0.8
V
CC
+ 1
0.5
Units
μA
μA
mA
mA
μA
μA
mA
V
V
V
V
mA
mA
mA
I
PD
I
OS
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
Note:
Output low current
Output high current
Ind.
Com., Ind.
1. All I
CC
parameters measured with outputs open
3
0425H–PLD–3/11
Figure 3.
AC waveforms
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
Table 3-1.
AC characteristics
-5
-7
Max
5
3
1
3
0
6
3
142
166
166
2
2
2
1.5
6
5
5
5
3
2
2
1.5
4
2
5
0
8
4
100
125
125
9
9
6
6
3
2
2
1.5
Min
3
Max
7.5
3
5
2
7.5
0
12
6
68
74
83
10
10
10
10
Min
3
-10
Max
10
6
7
Units
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
Symbol
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
Parameter
Input or feedback to non-registered output
Clock to feedback
Clock to output
Input or feedback setup time
Input hold time
Clock period
Clock width
External feedback 1/(t
S
+ t
CO
)
Min
1
f
MAX
Internal feedback 1/(t
S
+ t
CF
)
No feedback 1/(t
P
)
t
EA
t
ER
t
PZX
t
PXZ
Input to output enable – product term
Input to output disable – product term
OE pin to output enable
OE pin to output disable
4
Atmel ATF16V8C
0425H–PLD–3/11
Atmel ATF16V8C
Table 3-2.
Power-down AC characteristics
(1)(2)(3)
-5
Symbol
t
IVDH
t
GVDH
t
CVDH
t
DHIX
t
DHGX
t
DHCX
t
DLIV
t
DLGV
t
DLCV
t
DLOV
Note:
Parameter
Valid Input before PD High
Valid OE before PD High
Valid Clock before PD High
Input Don’t Care after PD High
OE Don’t Care after PD High
Clock Don’t Care after PD High
PD Low to Valid Input
PD Low to Valid OE
PD Low to Valid Clock
PD Low to Valid Output
1. Output data is latched and held
2. HI-Z outputs remain HI-Z
3. Clock and input transitions are ignored
Min
5.0
0
0
5.0
5.0
5.0
5.0
15.0
15.0
20.0
Max
Min
7.5
0
0
7.5
7.5
7.5
7.5
20.0
20.0
25.0
-7
Max
Min
10
0
0
10
10
10
10
25
25
30
-10
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.
Input test waveforms and measurement levels:
t
R
, t
F
< 1.5ns (10% to 90%)
5.
Output test loads
5.0V
R1 = 200
OUTPUT
PIN
R2 = 200
CL = 50 pF
6.
Pin capacitance
Table 6-1.
Pin capacitance
Typ
C
IN
C
OUT
Note:
5
6
Max
8
8
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
0425H–PLD–3/11
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