DATASHEET
HS-26C31RH, HS-26C31EH
Radiation Hardened Quad Differential Line Driver
The Intersil HS-26C31RH, HS-26C31EH are quad differential
line drivers designed for digital data transmission over
balanced lines and meets the requirements of EIA standard
RS-422. Radiation hardened CMOS processing assures low
power consumption, high speed, and reliable operation in the
most severe radiation environments.
The HS-26C31RH, HS-26C31EH accept CMOS levels and converts
them to RS-422 compatible outputs. These circuits uses special
outputs that enable the drivers to power-down without loading
down the bus. Enable and disable pins allow several devices to be
connected to the same data source and addressed
independently.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD
5962-96663.
A “hot-link” is provided on our
homepage for downloading.
FN3401
Rev 7.00
May 23, 2013
Features
• Electrically screened to SMD #5962-96663
• QML qualified per MIL-PRF-38535 requirements
• 1.2 Micron radiation hardened CMOS
- Total dose up to . . . . . . . . . . . . . . . . . . . . . . . . 300kRAD(Si)
• Latchup free
• EIA RS-422 compatible outputs (except for IOS)
• CMOS inputs
• High impedance outputs when disabled or powered down
• Low power dissipation . . . . . . . . . . . . 2.75mW standby (max)
• Single 5V supply
• Low output impedance . . . . . . . . . . . . . . . . . . . . . .10or less
• Full -55°C to +125°C military temperature range
Applications
• Line transmitter for MIL-STD-1553 serial data bus
Ordering Information
ORDERING NUMBER
(Note 1)
5962F9666301QEC
5962F9666301QXC
5962F9666301VEC
5962F9666301VXC
HS1-26C31RH/PROTO
HS0-26C31RH/SAMPLE
HS9-26C31RH/PROTO
5962F9666301V9A
5962F9666303VEC
5962F9666303VXC
5962F9666303V9A
5962F9666301VYC
HS9G-26C31RH/PROTO
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. The lid of these packages are connected to the ground pin of the device.
INTERNAL
MKT. NUMBER
HS1-26C31RH-8
HS9-26C31RH-8
HS1-26C31RH-Q
HS9-26C31RH-Q
HS1-26C31RH/PROTO
HS0-26C31RH/SAMPLE
HS9-26C31RH/PROTO
HS0-26C31RH-Q
HS1-26C31EH-Q
HS9-26C31EH-Q
HS0-26C31EH-Q
HS9G-26C31RH-Q (Note 2)
Q 5962F96 66301VYC
Q 5962F96 66303VEC
Q 5962F96 66303VXC
HS9- 26C31RH/PROTO
PART
MARKING
Q 5962F96 6630QEC
Q 5962F96 66301QXC
Q 5962F96 66301VEC
Q 5962F96 66301VXC
HS1- 26C31RH/PROTO
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(Pb-Free)
16 LD SBDIP
16 LD FLATPACK
16 LD SBDIP
16 LD FLATPACK
16 LD SBDIP
Die
16 LD FLATPACK
Die
16 LD SBDIP
16 LD FLATPACK
Die
16 LD FLATPACK
16 LD FLATPACK
K16.A
K16.A
D16.3
K16.A
PKG.
DWG. #
D16.3
K16.A
D16.3
K16.A
D16.3
HS9G-26C31RH/PROTO (Note 2) HS9G-26C31RH/PROTO
FN3401 Rev 7.00
May 23, 2013
Page 1 of 3
HS-26C31RH, HS-26C31EH
Pin Configurations
HS1-26C31RH, HS1-26C31EH
(16 LD SBDIP) CDIP2-T16
TOP VIEW
AIN 1
AO 2
AO 3
ENABLE 4
BO 5
BO 6
BIN 7
GND 8
16 VDD
15 DIN
14 DO
13 DO
12 ENABLE
11 CO
10 CO
9 CIN
AIN
AO
AO
ENABLE
BO
BO
BIN
GND
HS9-26C31RH, HS9-26C31EH
(16 LD FLATPACK) CDFP4-F16
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
DIN
DO
DO
ENABLE
CO
CO
CIN
Logic Diagram
ENABLE
ENABLE
DIN
CIN
BIN
AIN
DO DO
CO CO
BO BO
AO AO
© Copyright Intersil Americas LLC 2011-2013. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see
www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at
www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
FN3401 Rev 7.00
May 23, 2013
Page 2 of 3
HS-26C31RH, HS-26C31EH
Die Characteristics
DIE DIMENSIONS:
96.5 mils x 195 mils x 21 mils
(2450 x 4950)
Substrate:
AVLSI1RA
Backside Finish:
Silicon
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 10k
Å
±1k
Å
Metallization:
M1: Mo/TiW
Thickness: 5800
Å
M2: Al/Si/Cu (Top)
Thickness: 10k
Å
±1k
Å
ASSEMBLY RELATED INFORMATION:
Substrate Potential (Powered Up):
V
DD
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0x10
5
A/cm
2
Bond Pad Size:
110µmx100µm
Metallization Mask Layout
HS-26C31RH, HS-26C31EH
(16) VDD
(16) VDD
(15) DIN
(14) DO
(13) DO
(12) ENABLE
(11) CO
(10) CO
CIN (9)
(1) AIN
AO (2)
AO (3)
ENABLE (4)
BO (5)
BO (6)
BIN (7)
GND (8)
FN3401 Rev 7.00
May 23, 2013
GND (8)
Page 3 of 3
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