EEWORLDEEWORLDEEWORLD

Part Number

Search

BS62LV2007HCP70

Description
Standard SRAM, 256KX8, 70ns, CMOS, PBGA36
Categorystorage    storage   
File Size242KB,8 Pages
ManufacturerBrilliance
Environmental Compliance
Download Datasheet Parametric Compare View All

BS62LV2007HCP70 Overview

Standard SRAM, 256KX8, 70ns, CMOS, PBGA36

BS62LV2007HCP70 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerBrilliance
package instructionFBGA, BGA36,6X8,30
Reach Compliance Codeunknown
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PBGA-B36
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width8
Humidity sensitivity level3
Number of terminals36
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA36,6X8,30
Package shapeRECTANGULAR
Package formGRID ARRAY, FINE PITCH
Parallel/SerialPARALLEL
power supply3/5 V
Certification statusNot Qualified
Maximum standby current5e-7 A
Minimum standby current1.5 V
Maximum slew rate0.035 mA
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
DESCRIPTION
BS62LV2007
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns(Max.) at Vcc = 3.0V
-10
100ns(Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
The BS62LV2007 is a high performance , very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2007 is available in the JEDEC standard 36 ball Mini
BGA 6x8 mm.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=
3.0V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
Vcc=
Vcc=
5.0V
3.0V
(I
CC
, Max)
Vcc=
Vcc=
5.0V
3.0V
PKG
TYPE
BS62LV2007HC
0
O
C to +70
O
C
2.4V ~5.5V
-40
O
C to +85
O
C
70/100
6 uA
0.7 uA
35 mA
20 mA
BGA-36-
0608
BS62LV2007HI
70/100
25 uA
1.5 uA
40 mA
25 mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A13
A17
A15
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
Control
Address Input Buffer
8
Data
Output
Buffer
8
CE1
CE2
WE
OE
Vdd
Gnd
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV2007
1
Revision 2.1
Jan.
2004

BS62LV2007HCP70 Related Products

BS62LV2007HCP70 BS62LV2007HIP10 BS62LV2007HIG70 BS62LV2007HI10
Description Standard SRAM, 256KX8, 70ns, CMOS, PBGA36 Standard SRAM, 256KX8, 100ns, CMOS, PBGA36, MINIBGA-36 Standard SRAM, 256KX8, 70ns, CMOS, PBGA36 Standard SRAM, 256KX8, 100ns, CMOS, PBGA36
Is it Rohs certified? conform to conform to conform to incompatible
package instruction FBGA, BGA36,6X8,30 LFBGA, BGA36,6X8,30 FBGA, BGA36,6X8,30 FBGA, BGA36,6X8,30
Reach Compliance Code unknown unknown unknown unknown
Maximum access time 70 ns 100 ns 70 ns 100 ns
I/O type COMMON COMMON COMMON COMMON
JESD-30 code R-PBGA-B36 R-PBGA-B36 R-PBGA-B36 R-PBGA-B36
memory density 2097152 bit 2097152 bit 2097152 bit 2097152 bit
Memory IC Type STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM
memory width 8 8 8 8
Humidity sensitivity level 3 3 3 3
Number of terminals 36 36 36 36
word count 262144 words 262144 words 262144 words 262144 words
character code 256000 256000 256000 256000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 70 °C 85 °C 85 °C 85 °C
Minimum operating temperature - -40 °C -40 °C -40 °C
organize 256KX8 256KX8 256KX8 256KX8
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code FBGA LFBGA FBGA FBGA
Encapsulate equivalent code BGA36,6X8,30 BGA36,6X8,30 BGA36,6X8,30 BGA36,6X8,30
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, FINE PITCH GRID ARRAY, FINE PITCH
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL
power supply 3/5 V 3/5 V 3/5 V 3/5 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum standby current 5e-7 A 5e-7 A 5e-7 A 5e-7 A
Minimum standby current 1.5 V 1.5 V 1.5 V 1.5 V
Maximum slew rate 0.035 mA 0.04 mA 0.04 mA 0.04 mA
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form BALL BALL BALL BALL
Terminal pitch 0.75 mm 0.75 mm 0.75 mm 0.75 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM
Base Number Matches - 1 1 1
DSP-Sitara course progress has always been 50%, please come in!!!
For those who have always reached 50% of the progress, is it because they click on the opening in the picture above every time, and only reach 50% of the progress after watching the whole video? Techn...
maylove DSP and ARM Processors
430 interrupt nesting problem
The following points should be noted about the interrupt nesting of MSP430: 1) 430 defaults to closing interrupt nesting, unless you open the general interrupt EINT again in an interrupt program; 2) W...
KAIKAI1 Microcontroller MCU
Realization of measuring signal time interval using LabVIEW
Abstract Taking two signals as an example, this paper elaborates on the methods of using LabVIEW software platform to measure the time interval of signals in a virtual instrument manner for different ...
安_然 Test/Measurement
Question about FPGA loading method, urgent!
Dear seniors, FPGA adopts parallel loading method. Now CPLD has an external FLASH. It is required to use CPLD to control the loading timing, read the code from FLASH and send it to FPGA. How should CP...
duolakk FPGA/CPLD
BlueMS apk v3.6 download
The latest version of ST BlueMS apk, suitable for BlueCoin, SensorTile, X-Nucleo series development boards is not suitable for [url=https://bbs.eeworld.com.cn/thread-608692-1-1.html][color=#000000]STE...
朵拉A萌 ST - Low Power RF
Comparison and implementation of ARM startup code.
Comparison and implementation of ARM startup code....
ptwhero86 MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1046  1578  1791  2111  2001  22  32  37  43  41 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号