Single 80A/75VDC fast acting fuse; located the input “-48VIN” connection.
Weight
1.11kg.
1
Abnormal operation limited to 96hrs continuous and for not more than 15 days in any one year
AIRFLOW CHARACTERISTICS P-Q Curves
Front to Back models
q
Back to Front Models
Internal PSU fan speed 100% Duty Cycle
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D1U54-D-2000-12-HBxC.A01.D08 Page 2 of 8
D1U54-D-2000-12-HBxC Series
54mm 1U Front End DC-DC Power Supply Converter
PROTECTION CHARACTERISTICS
Output
Parameter
Voltage
Over temperature (intake)
Conditions
Min.
Typ.
65
Max.
15.0
217
15.0
4.50
6.0
5.0
4.0
5.0
Units
°C
Vdc
Adc
Vdc
A
Vdc
A
Vdc
A
Shutdown and auto-recovery, main output both
BF &
FB
Airflows
Main 12V Output; latching
1
(12VSB maintains operation)
13.0
Overvoltage
Main 12V
Overcurrent
Five (5) “hiccup” auto recovery cycles, followed by a latched shutdown
1
184
1
13.0
Overvoltage
Latching (both outputs shutdown).
12VSB
Overcurrent
Sustained “hiccup” auto recovery cycles until overcurrent is removed
3.1
Overvoltage
Latching
1
(both outputs shutdown).
5.4
5VSB
Overcurrent
Sustained “hiccup” auto recovery cycles until overcurrent is removed
3.1
Overvoltage
Latching
1
(both outputs shutdown).
3.6
3.3VSB
Overcurrent
Sustained “hiccup” auto recovery cycles until overcurrent is removed
3.1
1
Latch-off condition requires elimination of fault condition then recycling of either the DC input source or PS_ON signal to restore operation.
ISOLATION CHARACTERISTICS
Parameter
Insulation Safety Rating / Test Voltage
Isolation
EMISSIONS AND IMMUNITY
Characteristic
Conducted Emissions
ESD Immunity
Radiated Field Immunity
Electrical Fast Transients/Burst
Surge Immunity
RF Conducted Immunity
Conditions
Input to Output - Basic
Input to Chassis - Basic
Output to Chassis
Min.
1500
1500
500
Typ.
Max.
Units
Vdc
Vdc
Vdc
Standard
FCC 47 CFR
Part15/CISPR22/EN55032
IEC/EN 61000-4-2
IEC/EN 61000-4-3
IEC/EN 61000-4-4
IEC/EN 61000-4-5
Compliance
Class A with 6dB margin
3
±8KV Contact; ±15KV air discharge; Criteria A
10V/m, 1KHz, 80% AM, 80MHz to 1GHz Criteria A
Level 2 (1kV) criteria A
1
Level 2 500V DM 1kV CM, criteria A
1
IEC/EN 61000-4-6
Level 2,
3Vrms, 1KHz, 80% AM, 150kHz to 80MHz
criteria A
NEBS GR-1089-CORE.i07
Meets the applicable transients of GR-1089-CORE.I07 for DC Input source.
Voltage Dips, Interruptions
ATIS-600315.208
Meets applicable transients of ATIS-600315.2018
1
Measured at power module DC input connector
2
Installed in End User system and contingent upon final system design
3
Radiated performance designed to meet Class A limits; however contingent on deployment; final qualification and certification testing to be performed by End User in system installation
STATUS INDICATORS AND CONTROL SIGNALS (BICOLOUR LED)
Condition
Standby - ON; Main output - OFF; DC PRESENT
Standby - ON; Main output – ON, No faults present
Fault Detected: Main output, VSB output, Fan, overtemperature, input overvoltage (Note: coincides with setting of PMBus
Status_Register bit flag(s))
DC Input absent and/or no I2C slave address detected (See
Multi-function signal and is configured as one of the following:
DC_OK (Default setting at initial power up):
Output is driven high when input source is available and within acceptable limits. The output is driven low to indicate loss of
input power.
Interface Details
DC_OK
Pulled up via 511R to internal 5V
bias supply and pulled down to DC
Return via 10K OHM resistor.
DC_OK (Default)/
RAPID_ON
Output
PW_OK
(Output OK)
Output
SMB_ALERT
Output
(FAULT/WARNING)
PRESENT_L
(Power Supply
Absent)
PS_ON
Output
Input
RAPID_ON:
RAPID_ON is a two state analog signal forms the cold redundant bus with up to four (4) load connected PSUs. This signal is
Pulled 511R to 5V internal bias
TM
used exclusively by the PSU for cold redundant mode operation, and is configured via PMBus ; see
ACAN-80 and 89
for details supply of the ACTIVE & MASTER
PSU; Pull-Down = 10K.
+
wiring diagram.
Bus voltage reduces with the QTY
of bus connected power supplies
Rapid_ON signal/bus provides these three functions:
Pull-up bus voltage: Bus pull-up is provided by the single PSU or the first PSU assigned the roll of “ACTIVE & MASTER” aka
“COLD_REDUNDANT ACTIVE”. More than one PSU can be assigned as “ACTIVE” only the first PSU assigned this roll provides
the pull-up path and is why this PSU is referred to as the “Master”.
Each bus connected PSU drives the Rapid_ON bus low when any fault is detected.
Each bus connected PSU powers on its main output rapidly within 100µS after detection of LOW state.
Note: “Rapid_ON” pin configuration is retained once setup via PMBus
TM
, even if Input power is recycled and remains the new
default setting until commanded to INPUT_OK via PMBus
TM
.
The signal is asserted, driven high, by the power supply to indicate that the main output is valid. If the main output fails, the
Pulled up internally via 10K to VDD.
PW_OK signal will de-assert and is driven low. The PW_OK output is driven low to indicate that the Main output is outside of A logic high >2.0Vdc
lower limit of regulation
A logic low <0.8Vdc
Driven low by internal CMOS buffer
(open drain output).
The signal output is driven low to indicate that the power supply has detected a warning/fault, and any status register bits
Pulled up internally via 10K to VDD.
flagged (except Status_CML). It is intended to alert the system accordingly.
A logic high >2.0Vdc
A logic low <0.8Vdc
This output shall be driven high when the power is operating correctly (within specified limits).
The signal will revert to a high level when the warning/fault stimulus (that originally caused the alert) is removed.
Driven low by internal CMOS buffer
The LED indicator(s) mirrors this alert pin.
(open drain output).
The signal is used to detect the presence (installed) of a PSU by the host system. The signal is connected to PSU logic SGND
Passive connection to
within the power module.
+VSB_Return.
A logic low <0.8Vdc
This signal is pulled up internally to the internal housekeeping supply (within the power supply). The power supply main 12VDC Pulled up internally via 10K to VDD.
output will be enabled when this signal is pulled low to +VSB_Return.
A logic high >2.0Vdc
In the low state the signal input shall not source more than 1mA of current. The 12VDC output will be disabled when the input A logic low <0.8Vdc
Input is via CMOS Schmitt trigger
is driven higher than 2.4V, or open circuited. Cycling this signal shall clear latched fault conditions. (Power Supply
buffer.
Enable/Disable “Mate Last, Break First” (MLBF) Signal
A multifunction signal used to detect presence in the system and to set the slave device address.
When this pin is left open all power module operation will be inhibited and a default slave address will be assigned (0x80h) to
allow communication with slave devices.
When the power module is inserted into a system this pin will be pulled (via a suitable external select resistor to +VSB_Return,
and in conjunction with an internal resistor divider chain, shall configure the required slave (EEPROM and microprocessor)
address used for digital communications. Back to
LED Status Table;
See ADDR
selection table below
A serial communications line compatible with PMBus
TM
Power Systems Management Protocol Part 1 – General Requirements
Rev 1.2.
No additional internal capacitance is added that would affect the speed of the bus.
The signal is provided with a series isolator device to disconnect the internal power supply bus in the event that the power
module is unpowered.
Remote sense connections intended to be connected at and sense the voltage at the point of load.
The voltage sense will interact with the internal module regulation loop to compensate for voltage drops due to connection
resistance between the output connector and the load.
If remote sense compensation is not required then the voltage can be configured for local sense by:
1.
V1_SENSE directly connected to power blades 4 to 6 (inclusive)
2.
V1_SENSE_RTN directly connected to power blades 1 to 3 (inclusive)
The current sharing signal is connected between sharing units (forming an ISHARE bus). It is an input and/or an output (bi-
directional analog bus) as the voltage on the line controls the current share between sharing units. A power supply will respond
to a change in this voltage but a power supply can also change the voltage depending on the load drawn from it. On a single
unit the voltage on the pin (and the common ISHARE bus would read 8VDC at 100% load (module capability). For two identical
units sharing the same 100% load this would read 4VDC for perfect current sharing (i.e. 50% module load capability per unit).
Analogue (DC) voltage level
between the limits of 0Vdc and
+3.3Vdc.
ADDR/
PS_INHIBIT
Input
SCL (Serial Clock)
SDA (Serial Data)
V1_SENSE &
V1SENSE_RTN
Both
Input
Pulled up via 5.11K to internal
3.3VDC
VIL is 0.8V maximum
VOL is 0.4V maximum
VIH is 2.1V minimum
Compensation for up to 0.12Vdc
total connection drop (output and
return connections).
ISHARE
Both
Analogue voltage:
+8V maximum;
13.1K to
Main 12V_RTN
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D1U54-D-2000-12-HBxC.A01.D08 Page 4 of 8
D1U54-D-2000-12-HBxC Series
54mm 1U Front End DC-DC Power Supply Converter
ADDR SELECTION TABLE
ADDR pin (D4) resistor
Power Supply Main Controller
to GND (K-ohm)*
(Serial Communications Slave Address)
0.82
0xB0
2.7
0xB2
5.6
0xB4
8.2
0xB6
15
0xB8
27
0xBA
56
0xBC
180
0xBE
OPEN/PS_INHIBIT
0x80
* The resistor shall be no more than +/-5% tolerance
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