PI3VDP411LS
Features
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Description
Pericom Semiconductor’s PI3VDP411LS provides the ability to
use a Dual-mode DP transmitter in HDMI mode. This
fl
exibility
provides the user a choice of how to connect to their favorite
display. All signal paths accept AC coupled video signals. The
PI3VDP411LS converts this AC coupled signal into an HDMI
rev 1.3 compliant signal with proper signal swing. This conver-
sion is automatic and transparent to the user.
The PI3VDP411LS supports up to 2.5Gbps, which provides 12-
bits of color depth per channel, as indicated in HDMI rev 1.3.
• Converts low-swing AC coupled differential input to HDMI
rev 1.3 compliant open-drain current steering Rx terminated dif-
ferential output
• HDMI level shifting operation up to 2.5Gbps per lane
(250MHz pixel clock)
• Integrated 50-ohm termination resistors for AC-coupled dif-
ferential inputs.
• Enable/Disable feature to turn off TMDS outputs to enter low-
power state.
• Output slew rate control on TMDS outputs to minimize EMI.
• Transparent operation: no re-timing or configuration required.
• 3.3 Power supply required.
• Integrated ESD protection to 8kV contact on all high speed
I/O pins (IN_x and OUT_x) per IEC61000-4-2 test spec, level 4
• DDC level shifters from 5V from sink side down to 3.3V on
source side
• Level shifter for HPD signal from HDMI/DVI connector
• Integrated pull-down on HPD_sink input guarantees "input
low" when no display is plugged in
• Packaging (Pb-Free & Green available)
– 48 TQFN, 7mm × 7mm (ZDE)
– 48 TQFN, 7mm x 7mm (ZBE)
– 42 TQFN, 9mm × 3.5mm (ZHE)
Pin Configuration
42-Pin TQFN (ZHE)
HPD_SINK
SDA_SINK
SCL_SINK
GND
EQ_1
GND
48-Pin TQFN (ZDE/ZBE)
HPD_SINK
SDA_SINK
SCL_SINK
EQ_0
DDC_EN
GND
VDD
GND
VDD
DDC_EN
EQ_0
GND
IN_D1-
IN_D1+
VDD
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VDD
IN_D4-
IN_D4+
GND
VDD
OC_0
1
38
42 41 40 39
2
37
3
36
4
35
5
34
6
33
7
32
8
31
GND
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
18 19 20 21 23
17
22
HPD_Source
SDA_Source
OC_1
OC_2
VDD
OE#
GND
OUT_D1-
OUT_D1+
VDD
OUT_D2-
OUT_D2+
GND
OUT_D3-
OUT_D3+
VDD
OUT_D4-
OUT_D4+
GND
VDD
SCL_Source
GND
IN_D1-
IN_D1+
VDD
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VDD
IN_D4-
IN_D4+
37
36
35
34
33
32
31
30
29
28
27
26
OE#
25
24
23
22
21
20
GND
OUT_D1-
OUT_D1+
VDD
OUT_D2-
OUT_D2+
GND
OUT_D3-
OUT_D3+
VDD
OUT_D4-
OUT_D4+
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
GND
19
18
17
16
15
14
13
12
HPD_SOURCE
GND
OC_0
OC_1
GND
SDA_SOURCE
OC_3
VDD
VDD
OC_2(REXT )
08-0294
SCL_SOURCE
1
PS8913D
GND
11/05/08
PI3VDP411LS
Display Port Redriver w/ Level Conversion feature for
DVI/HDMI interoperability
Block Diagram
OE#
0V
INx_D4+
INx_D4-
OUTx_D4+
OUTx_D4-
Rx
0V
INx_D3+
INx_D3-
OUTx_D3+
OUTx_D3-
Rx
0V
INx_D2+
INx_D2-
OUTx_D2+
OUTx_D2-
Rx
0V
INx_D1+
INx_D1-
OUTx_D1+
OUTx_D1-
Rx
HPD_SOURCE
HPD
HPD_SINK
DDC_EN (0V TO 3.3V)
SCL_SOURCE
SCL_SINK
SDA_SOURCE
SDA_SINK
(times 2)
x = 1 or 2
08-0294
2
PS8913D
11/05/08
PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this speci
fi
cation
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Maximum Ratings
(Above which useful life may be im-
paired. For user guidelines, not tested.)
Storage Temperature.....................................–65°C to +150°C
Supply Voltage to Ground Potential.............–0.5V to +5V
DC Input Voltage..........................................–0.5V to V
DD
DC Output Current .......................................120mA
Power Dissipation .........................................1.0W
Table 2: Signal Descriptions
Pin Name
Type
OE#
5.5V tolerant low-voltage
single-ended input
Description
Enable for level shifter path
OE#
IN_D Termination OUT_D Outputs
1
>100KΩ
High-Z
0
50Ω
Active
Low-swing diff input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4–.
Low-swing diff input from GMCH PCIE outputs.
IN_D4– makes a differential pair with IN_D4+.
Low-swing diff input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3–.
Low-swing diff input from GMCH PCIE outputs.
IN_D3– makes a differential pair with IN_D3+.
Low-swing diff input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2–.
Low-swing diff input from GMCH PCIE outputs.
IN_D2– makes a differential pair with IN_D2+.
Low-swing diff input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1–.
Low-swing diff input from GMCH PCIE outputs.
IN_D1– makes a differential pair with IN_D1+.
HDMI 1.3 compliant TMDS output. OUT_D4+
makes a differential output signal with OUT_D4–.
HDMI 1.3 compliant TMDS output. OUT_D4–
makes a differential output signal with OUT_D4+.
HDMI 1.3 compliant TMDS output. OUT_D3+
makes a differential output signal with OUT_D3–.
HDMI 1.3 compliant TMDS output. OUT_D3–
makes a differential output signal with OUT_D3+.
(Continued)
IN_D4+
IN_D4–
IN_D3+
IN_D3–
IN_D2+
IN_D2–
IN_D1+
IN_D1–
OUT_D4+
OUT_D4–
OUT_D3+
OUT_D3–
Differential input
Differential input
Differential input
Differential input
Differential input
Differential input
Differential input
Differential input
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
08-0294
3
PS8913D
11/05/08
PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Pin Name
OUT_D2+
OUT_D2–
OUT_D1+
OUT_D1–
HPD_SINK
Type
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
5V tolerance single-ended input
Description
HDMI 1.3 compliant TMDS output. OUT_D2+ makes
a differential output signal with OUT_D2–.
HDMI 1.3 compliant TMDS output. OUT_D2– makes
a differential output signal with OUT_D2+.
HDMI 1.3 compliant TMDS output. OUT_D1+ makes
a differential output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes
a differential output signal with OUT_D1+.
HPD_SOURCE
SCL_SOURCE
SDA_SOURCE
SCL_SINK
SDA_SINK
DDC_EN
Low Frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage High
indicates "plugged" state; voltage low indicated
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm put-down resistor.
3.3V single-ended output
HPD_SOURCE: 0V to 3.3V (nominal) output signal.
This is level-shifted version of the HPD_SINK signal.
Single-ended 3.3V open-drain
3.3V DDC Data I/O. Pulled up by external termina-
DDC I/O
tion to 3.3V. Connected to SCL_SINK through volt-
age-limiting integrated NMOS passgate.
3.3V DDC Data I/O. Pulled up by external termination
Single-ended 3.3V open-drain
DDC I/O
to 3.3V. Connected to SDA_SINK through voltage-
limiting integrated NMOS passgate.
Single-ended 5V open-drain
5V DDC Clock I/O. Pulled up by external termination
DDC I/O
to 5V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS passgate.
Single-ended 5V open-drain
5V DDC Data I/O. Pulled up by external termination
DDC I/O
to 5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS passgate.
5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter
gates. (May be implemented as a bias voltage connec-
tion to the DDC pass gates themselves.)
DDC_EN
Passgate
0V
Disabled
3.3V
Enabled
3.3V DC Supply
3.3V single-ended control input
3.3V ± 10%
Acceptable connections to OC_1 (REXT) pin are: Re-
sistor to GND; Resistor to 3.3V; NC. (Resistor should
be 0-ohm).
VDD
OC_2
(REXT)
08-0294
4
PS8913D
11/05/08
PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Pin Name
OC_3
OC_0
OC_1
EQ_0
EQ_1
Type
Analog connection to external
component or supply
Output and Input jitter elimina-
tion control
Description
Acceptable connections to OC_3 pin are: short to
3.3V or to GND; NC.
Control pins are to enable Jitter elimination features.
For normal operation these pins are tied GND or to
VDD. Please see the truth tables for more information.
Truth Table 1
OC_3
(2)
OC_2
(1)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OC_1
(1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
OC_0
(1)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Vswing
(mV)
500
600
750
1000
500
500
500
500
400
400
400
400
1000
1000
1000
1000
Pre/De-
emphasis
0
0
0
0
0
1.5dB
3.5dB
6dB
0
3.5dB
6dB
9dB
0
-3.5dB
-6dB
-9dB
Truth Table 2
EQ_1
(2)
EQ_0
(1)
0
0
1
1
0
1
0
1
Equalization
@ 1.25GHz
(dB)
3
6
9
12
Notes:
1) These signals have internal 100kΩ pull-ups.
2) For 42-TQFN package, these signals are internally connected to GND directly.
For 48-TQFN package, these signals have internal 100kΩ pull-ups, with external connection.
08-0294
5
PS8913D
11/05/08
京公网安备 11010802033920号
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