PI7C9X111SL datasheet, PDF - EEWORLD Datasheet

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PI7C9X111SL: DescriptionPCI BUS CONTROLLER, PQFP128; Categorysemiconductor The embedded processor and controller; File Size492KB，78 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/

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PI7C9X111SL Overview

PCI BUS CONTROLLER, PQFP128

PI7C9X111SL Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	128
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.1 V
Minimum supply/operating voltage	0.9000 V
Rated supply voltage	1 V
External data bus width	32
Processing package description	14 × 14 MM, 0.40 MM PITCH, Green, MS-026, LQFP-128
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
packaging shape	SQUARE
Package Size	FLATPACK, HEAT SINK/SLUG, 低 PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.4000 mm
terminal coating	MATTE Tin
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
Address bus width	32
Maximum FCLK clock frequency	100 MHz
Microprocessor type	PCI bus controller

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PI7C9X111SL

PCI Express-to-PCI

Reversible Bridge

Revision 1.5

3545 North 1

Street, San Jose, CA 95134

Phone: 1-877-PERICOM (1-877-737-4266)

FAX: 1-408-435-1100

Internet:

http://www.pericom.com

PI7C9X111SL

PCIe-to-PCI Reversible Bridge

TABLE OF CONTENTS

INTRODUCTION ........................................................................................................................ 10

1.1

1.2

1.3

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

3.1

3.2

PCI EXPRESS FEATURES................................................................................................... 10

PCI FEATURES..................................................................................................................... 11

GENERAL FEATURES ........................................................................................................ 11

SIGNAL TYPES .................................................................................................................... 12

PCI EXPRESS SIGNALS ...................................................................................................... 12

PCI SIGNALS ........................................................................................................................ 12

MODE SELECT AND STRAPPING SIGNALS................................................................... 15

JTAG BOUNDARY SCAN SIGNALS ................................................................................. 15

MISCELLANEOUS SIGNALS ............................................................................................. 15

POWER AND GROUND PINS............................................................................................. 15

PIN ASSIGNMENTS............................................................................................................. 16

FUNCTIONAL MODE SELECTION ................................................................................... 17

PIN STRAPPING ................................................................................................................... 17

PIN DEFINITIONS...................................................................................................................... 12

MODE SELECTION AND PIN STRAPPING.......................................................................... 16

FORWARD AND REVERSE BRIDGING................................................................................ 18

PCI EXPRESS FUNCTIONAL OVERVIEW........................................................................... 20

5.1

5.2

TLP STRUCTURE................................................................................................................. 20

VIRTUAL ISOCHRONOUS OPERATION.......................................................................... 20

CONFIGURATION REGISTER MAP.................................................................................. 21

PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ........................................... 23

PCI CONFIGURATION REGISTERS.................................................................................. 25

VENDOR ID – OFFSET 00h ................................................................................................................ 25

DEVICE ID – OFFSET 00h.................................................................................................................. 25

COMMAND REGISTER – OFFSET 04h .............................................................................................. 25

PRIMARY STATUS REGISTER – OFFSET 04h................................................................................... 26

REVISION ID REGISTER – OFFSET 08h ........................................................................................... 27

CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 27

CACHE LINE SIZE REGISTER – OFFSET 0Ch.................................................................................. 28

PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 28

PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 28

RESERVED REGISTERS – OFFSET 10h TO 17h................................................................................ 28

PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 28

SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 28

SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 28

SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 29

I/O BASE REGISTER – OFFSET 1Ch.................................................................................................. 29

I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................. 29

CONFIGURATION REGISTER ACCESS............................................................................... 21

6.1

6.2

6.3

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

6.3.10

6.3.11

6.3.12

6.3.13

6.3.14

6.3.15

6.3.16

Page 4 of 78

Pericom Semiconductor - Confidential

Feb, 2010, Revision 1.5

PI7C9X111SL

PCIe-to-PCI Reversible Bridge

6.3.17

6.3.18

6.3.19

6.3.20

6.3.21

6.3.22

6.3.23

6.3.24

6.3.25

6.3.26

6.3.27

6.3.28

6.3.29

6.3.30

6.3.31

6.3.32

6.3.33

6.3.34

6.3.35

6.3.36

6.3.37

6.3.38

6.3.39

6.3.40

6.3.41

6.3.42

6.3.43

6.3.44

6.3.45

6.3.46

6.3.47

6.3.48

6.3.49

6.3.50

6.3.51

6.3.52

6.3.53

6.3.54

6.3.55

6.3.56

6.3.57

6.3.58

6.3.59

6.3.60

6.3.61

6.3.62

6.3.63

6.3.64

6.3.65

6.3.66

6.3.67

6.3.68

SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 29

MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 30

MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 30

PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h......................................................... 30

PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h........................................................ 31

PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 32

PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch............................................... 32

I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h......................................................................... 32

I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 32

CAPABILITY POINTER – OFFSET 34h .............................................................................................. 32

EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 32

INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................... 32

INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 33

BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 33

PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 34

CHIP CONTROL 0 REGISTER – OFFSET 40h................................................................................... 35

RESERVED REGISTER – OFFSET 44h............................................................................................... 37

ARBITER ENABLE REGISTER – OFFSET 48h................................................................................... 37

ARBITER MODE REGISTER – OFFSET 48h...................................................................................... 37

ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 38

RESERVED REGISTERS – OFFSET 4Ch ............................................................................................ 38

MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h.................................... 38

MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h .................................... 38

MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h ...................................... 39

MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch ................................... 39

MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h .................................... 39

MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h ................................................ 39

EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h.................................................... 39

UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 40

RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 41

EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h........................................... 41

RESERVED REGISTER – OFFSET 74h............................................................................................... 42

GPIO DATA AND CONTROL REGISTER – OFFSET 78h.................................................................. 42

RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 42

PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 42

NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 42

PCI-X SECONDARY STATUS REGISTER – OFFSET 80h.................................................................. 42

PCI-X BRIDGE STATUS REGISTER – OFFSET 84h.......................................................................... 43

UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 43

DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 44

POWER MANAGEMENT ID REGISTER – OFFSET 90h.................................................................... 44

NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 44

POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 44

POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 45

PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 45

RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 46

CAPABILITY ID REGISTER – OFFSET A0h....................................................................................... 46

NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 46

SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 46

CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 46

SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................. 46

CAPABILITY ID REGISTER – OFFSET A8h....................................................................................... 47

Page 5 of 78

Pericom Semiconductor - Confidential

Feb, 2010, Revision 1.5

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