XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
APRIL 2011
REV. 1.0.0
GENERAL DESCRIPTION
The XR16M890
1
(M890) is a single-channel
Universal Asynchronous Receiver and Transmitter
(UART) with integrated level shifters and 128 bytes of
transmit and receive FIFOs.
For flexibility in a mixed voltage environment, the
M890 has 4 VCC pins. There is a VCC pin for the
core, a VCC pin for the UART signals, a VCC pin for
the CPU interface signals and a VCC pin for the
GPIO signals. The VCC pins for the UART, GPIO
and CPU interface signals allow for the M890 to
interface with devices operating at different voltage
levels eliminating the need for external voltage level
shifters.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection and
Address Byte Control features increase the
performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. In addition, the Fractional
Baud Rate Generator feature provides flexibility for
crystal/clock frequencies for generating standard and
non-standard baud rates.
The M890 has programmable transmit and receive
FIFO trigger levels, automatic hardware and software
flow control, and data rates of up to 24 Mbps. Power
consumption of the M890 can be minimized by
enabling the sleep mode.
The M890 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M890 has a selectable
Intel/Motorola/VLIO bus interface.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
Integrated Level Shifters on CPU interface, UART
and GPIO signals
•
Intel/Motorola/VLIO Bus Interface select
■
’0’ ns address setup/hold times
•
24 Mbps maximum UART data rate
•
Up to 16 GPIOs
•
128-Bytes TX and RX FIFOs
•
Programmable TX/RX trigger levels
•
TX/RX FIFO Level Counters
•
Independent TX/RX Baud Rate Generator
•
Fractional Baud Rate Generator
•
Auto RTS/CTS Hardware Flow Control
•
Auto XON/XOFF Software Flow Control
•
Auto RS-485 Half-Duplex Direction Control
•
Multidrop mode w/ Auto Address Detect (RX)
•
Multidrop mode w/ Address Byte Control (TX)
•
Sleep Mode with Automatic Wake-up
•
Infrared (IrDA 1.0 and 1.1) mode
•
1.62V to 3.63V supply operation
•
5V tolerant inputs
•
Crystal oscillator or external clock input
APPLICATIONS
•
Personal Digital Assistants (PDA)
•
Cellular Phones/Data Devices
•
Battery-Operated Devices
•
Global Positioning System (GPS)
•
Bluetooth
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
PIN DESCRIPTIONS
Pin Description
N
AME
QFN-32
P
IN
#
QFN-40 TQFP-48
T
YPE
PIN#
PIN#
D
ESCRIPTION
DATA BUS INTERFACE - Intel/Motorola
16/68#
32
1
1
I
Intel or Motorola Bus Select. This pin selects the 16 or 68 mode
when VLIO_EN is a logic 0. In the VLIO mode (VLIO_EN is a logic
1), this pin becomes the SLEEP/PWRDN# pin in the QFN-32 pack-
age.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will oper-
ate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface. This pin does not have
an internal pull-up or pull-down resistor.
A2
A1
A0
29
30
31
38
39
40
46
47
48
I
Address lines [2:0]. These 3 address lines select the internal regis-
ters in UART channel during a data bus transaction.
In the VLIO bus mode (details on next page):
■
■
■
A2 becomes ENIR#
A1 becomes ENRS485# in the QFN-32 package
A1 is an unused input on the TQFP-48 and QFN-40
packages and should be connected to GND
A0 becomes LLA#
■
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
8
7
6
5
4
3
2
1
13
9
8
7
6
5
4
3
2
16
9
8
7
6
5
4
3
2
10
I/O
Data bus lines [7:0] (bidirectional).
In the VLIO bus mode, D7:D0 becomes AD7:AD0.
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input should be connected to VCC.
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
This input is chip select (active low) to enable the device.
IOW#
(R/W#)
14
17
11
I
CS#
15
18
12
I
5
FPGA/CPLD
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