Philips Semiconductors
Product specification
Buffers with open-drain outputs
FEATURES
•
Wide supply voltage range from 1.65 V to 5.5 V
•
5 V tolerant input/output for interfacing with 5 V logic
•
High noise immunity
•
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• −24
mA output drive (V
CC
= 3.0 V)
•
CMOS low power consumption
•
Latch-up performance exceeds 250 mA
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5 V
•
Multiple package options
•
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PLZ
/t
PZL
PARAMETER
CONDITIONS
DESCRIPTION
74LVC2G07
The 74LVC2G07 is a high-performance, low-power,
low-voltage, Si-gate CMOS device superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 V or 5 V devices. This
feature allows the use of this device in a mixed
3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant
for slower input rise and fall time.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC2G07 provides two non-inverting buffers.
The output of the device is an open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
TYPICAL
3.5
ns
ns
ns
ns
ns
UNIT
propagation delay input nA to output nY V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
2.4
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
2.3
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
2.6
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Ω
1.5
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
2.5
6.5
pF
pF
2004 Sep 08
2
Philips Semiconductors
Product specification
Buffers with open-drain outputs
74LVC2G07
handbook, halfpage
handbook, halfpage
1
1A
1Y
6
1A
1
6
1Y
3
2A
2Y
4
2A
3
4
2Y
MNB092
MNB093
Fig.3 Logic symbol.
Fig.4 IEEE/IEC logic symbol.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
operating ambient temperature
input rise and fall times
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
active mode
V
CC
= 0 V; Power-down mode
CONDITIONS
0
0
0
−40
0
0
MIN.
1.65
MAX.
5.5
5.5
V
CC
5.5
+125
20
10
V
V
V
V
°C
ns/V
ns/V
UNIT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
T
stg
P
tot
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
2004 Sep 08
4
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
output source or sink current
V
CC
or GND current
storage temperature
power dissipation
T
amb
=
−40 °C
to +125
°C
V
I
< 0 V
note 1
V
O
< 0 V
active mode; notes 1 and 2
V
O
= 0 V to 6.5 V
CONDITIONS
−
−0.5
−
−0.5
−
−
−65
−
MIN.
−0.5
MAX.
+6.5
−50
+6.5
−50
+6.5
+6.5
50
±100
+150
300
V
mA
V
mA
V
V
mA
mA
°C
mW
UNIT
Power-down mode; notes 1 and 2
−0.5
Embedded System
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