CY62187EV30 MoBL
®
64-Mbit (4 M × 16) Static RAM
shy64-Mbit (4 M × 16) Static RAM
Features
■
Functional Description
The CY62187EV30 is a high performance CMOS static RAM
organized as 4 M words by 16-bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can also be put into standby mode when deselected
(CE
1
HIGH or CE
2
LOW or both BHE and BLE are HIGH). The
input and output pins (I/O
0
through I/O
15
) are placed in a high
impedance state when: deselected (CE
1
HIGH or CE
2
LOW),
outputs are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE
1
LOW, CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through
A
21
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
21
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the
Truth Table
on page
9 for a complete description of read and write modes.
Very high speed
❐
55 ns
Wide voltage range
❐
2.2 V to 3.7 V
Ultra low standby power
❐
Typical standby current: 8
A
❐
Maximum standby current: 48
A
Ultra low active power
❐
Typical active current: 7.5 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2,
and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 48-ball FBGA package
■
■
■
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 001-48998 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 18, 2012
CY62187EV30 MoBL
®
Logic Block Diagram
DATA-IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
4096K × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
A
21
CE
2
CE
1
Power down
Circuit
Document Number: 001-48998 Rev. *G
Page 2 of 15
CY62187EV30 MoBL
®
Contents
Pin Configuration ............................................................. 4
Product Portfolio .............................................................. 4
Maximum Ratings............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 6
Data Retention Characteristics ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Document Number: 001-48998 Rev. *G
Page 3 of 15
CY62187EV30 MoBL
®
Pin Configuration
Figure 1. 48-ball FBGA
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
A
18
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
A
19
A
8
3
A
0
A
3
A
5
A
17
A
21
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
Vcc
Vss
I/O
6
I/O
7
A
20
A
B
C
D
E
F
G
H
Product Portfolio
Power Dissipation
Product
V
CC
Range (V)
Speed
(ns)
Typ
[1]
55
7.5
Operating I
CC
(mA)
f = 1 MHz
Min
CY62187EV30LL
2.2
Typ
[1]
3.0
Max
3.7
Max
9
f = f
Max
Typ
[1]
45
Max
55
Standby I
SB2
(A)
Typ
[1]
8
Max
48
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document Number: 001-48998 Rev. *G
Page 4 of 15
CY62187EV30 MoBL
®
DC Input Voltage
[2, 3]
.................. –0.3 V to V
CC (max)
+ 0.3 V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch Up Current .................................................... > 200 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Supply Voltage to Ground
Potential........................................ –0.3 V to V
CC(max)
+ 0.3 V
DC Voltage Applied to Outputs
in High Z State
[2, 3]
....................... –0.3 V to V
CC(max)
+ 0.3 V
Operating Range
Device
CY62187EV30LL
Range
Ambient
Temperature
V
CC
[4]
Industrial –40 °C to +85 °C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB2 [7]
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
V
CC
operating supply
current
Automatic CE
power down
current—CMOS inputs
Test Conditions
2.2 V < V
CC
< 2.7 V
2.7 V < V
CC
< 3.7 V
2.2 V < V
CC
< 2.7 V
2.7 V < V
CC
< 3.7 V
2.2 V < V
CC
< 2.7 V
2.7 V < V
CC
< 3.7 V
2.2 V< V
CC
< 2.7 V
2.7 V < V
CC
< 3.7 V
GND < V
I
< V
CC
GND < V
O
< V
CC
, output disabled
f = f
Max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1 mA
55 ns
Min
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–1
–1
–
–
–
Typ
[5]
–
–
–
–
–
–
–
–
–
–
45
7.5
8
Max
–
–
0.4
0.4
V
CC
+ 0.3 V
V
CC
+ 0.3 V
0.6
0.8
[6]
+1
+1
55
9
48
Unit
V
V
V
V
V
V
V
V
A
A
mA
mA
A
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V or
(BHE and BLE) > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V, f = 0,
V
CC
= 3.7 V
Capacitance
Parameter
[8]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
Max
25
35
Unit
pF
pF
Notes
2. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
3. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
4. Full Device AC operation assumes a 100
s
ramp time from 0 to V
CC
(min) and 200
s
wait time after V
CC
stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
6. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions input LOW Voltage applied to the device must not be higher than 0.7 V.
7. Chip enables (CE
1
and CE
2
) and Byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-48998 Rev. *G
Page 5 of 15
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