74LVC3G04DP datasheet, PDF - EEWORLD Datasheet

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74LVC3G04DP: DescriptionTriple inverter; Categorylogic logic; File Size60KB，13 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/; Environmental Compliance

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74LVC3G04DP Overview

Triple inverter

74LVC3G04DP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	TSSOP, TSSOP8,.16
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G8
Load capacitance (CL)	50 pF
Logic integrated circuit type	INVERTER
MaximumI(ol)	0.024 A
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP8,.16
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
power supply	3.3 V
Prop。Delay @ Nom-Sup	5.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL

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74LVC3G04

Triple inverter

Rev. 01 — 4 May 2004

Product data sheet

1. General description

The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device

and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I

off

. The I

off

circuitry

disables the output, preventing the damaging backﬂow current through the device when it

is powered down.

The 74LVC3G04 provides three inverting buffers.

2. Features

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant outputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V).

ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

±24

mA output drive (V

= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

SOT505-2 and SOT765-1 package

Speciﬁed from

−40 °C

to +85

°C

and

−40 °C

to +125

°C.

74LVC3G04DP Related Products

	74LVC3G04DP	74LVC3G04	74LVC3G04DC
Description	Triple inverter	Triple inverter	LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8
Is it Rohs certified?	conform to	-	conform to
Maker	Philips Semiconductors (NXP Semiconductors N.V.)	-	Philips Semiconductors (NXP Semiconductors N.V.)
package instruction	TSSOP, TSSOP8,.16	-	TSSOP, TSSOP8,.12,20
Reach Compliance Code	unknown	-	unknown
JESD-30 code	R-PDSO-G8	-	R-PDSO-G8
Load capacitance (CL)	50 pF	-	50 pF
Logic integrated circuit type	INVERTER	-	INVERTER
MaximumI(ol)	0.024 A	-	0.024 A
Number of terminals	8	-	8
Maximum operating temperature	125 °C	-	125 °C
Minimum operating temperature	-40 °C	-	-40 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TSSOP	-	TSSOP
Encapsulate equivalent code	TSSOP8,.16	-	TSSOP8,.12,20
Package shape	RECTANGULAR	-	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL	-	TAPE AND REEL
power supply	3.3 V	-	3.3 V
Prop。Delay @ Nom-Sup	5.5 ns	-	5.5 ns
Certification status	Not Qualified	-	Not Qualified
Schmitt trigger	NO	-	NO
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	AUTOMOTIVE	-	AUTOMOTIVE
Terminal form	GULL WING	-	GULL WING
Terminal pitch	0.635 mm	-	0.5 mm
Terminal location	DUAL	-	DUAL

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