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74LVC3G04DC

Description
LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8
Categorylogic    logic   
File Size60KB,13 Pages
ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.)
Websitehttps://www.nxp.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

74LVC3G04DC Overview

LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8

74LVC3G04DC Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerPhilips Semiconductors (NXP Semiconductors N.V.)
package instructionTSSOP, TSSOP8,.12,20
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-G8
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.024 A
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP8,.12,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
power supply3.3 V
Prop。Delay @ Nom-Sup5.5 ns
Certification statusNot Qualified
Schmitt triggerNO
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
74LVC3G04
Triple inverter
Rev. 01 — 4 May 2004
Product data sheet
1. General description
The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC3G04 provides three inverting buffers.
2. Features
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
±24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
SOT505-2 and SOT765-1 package
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
s
s
s
s
s
s
s

74LVC3G04DC Related Products

74LVC3G04DC 74LVC3G04 74LVC3G04DP
Description LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8 Triple inverter Triple inverter
Is it Rohs certified? conform to - conform to
Maker Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.)
package instruction TSSOP, TSSOP8,.12,20 - TSSOP, TSSOP8,.16
Reach Compliance Code unknown - unknown
JESD-30 code R-PDSO-G8 - R-PDSO-G8
Load capacitance (CL) 50 pF - 50 pF
Logic integrated circuit type INVERTER - INVERTER
MaximumI(ol) 0.024 A - 0.024 A
Number of terminals 8 - 8
Maximum operating temperature 125 °C - 125 °C
Minimum operating temperature -40 °C - -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code TSSOP - TSSOP
Encapsulate equivalent code TSSOP8,.12,20 - TSSOP8,.16
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TAPE AND REEL - TAPE AND REEL
power supply 3.3 V - 3.3 V
Prop。Delay @ Nom-Sup 5.5 ns - 5.5 ns
Certification status Not Qualified - Not Qualified
Schmitt trigger NO - NO
Nominal supply voltage (Vsup) 3.3 V - 3.3 V
surface mount YES - YES
technology CMOS - CMOS
Temperature level AUTOMOTIVE - AUTOMOTIVE
Terminal form GULL WING - GULL WING
Terminal pitch 0.5 mm - 0.635 mm
Terminal location DUAL - DUAL

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