UPD4481321F9-C65-EQX datasheet, PDF

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UPD4481321F9-C65-EQX: DescriptionZBT SRAM, 256KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165; Categorystorage storage; File Size222KB，40 Pages; ManufacturerNEC Electronics

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UPD4481321F9-C65-EQX Overview

ZBT SRAM, 256KX32, 6.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

UPD4481321F9-C65-EQX Parametric

Parameter Name	Attribute value
Maker	NEC Electronics
Parts packaging code	BGA
package instruction	BGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	6.5 ns
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	8388608 bit
Memory IC Type	ZBT SRAM
memory width	32
Number of functions	1
Number of terminals	165
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX32
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD4481161, 4481181, 4481321, 4481361

8M-BIT ZEROSB

SRAM

FLOW THROUGH OPERATION

Description

The

PD4481161 is a 524,288-word by 16-bit, the

PD4481181 is a 524,288-word by 18-bit, the

PD4481321 is a

262,144-word by 32-bit and the

PD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD4481161,

PD4481181,

PD4481321 and

PD4481361 are optimized to eliminate dead cycles for read to

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

The

PD4481161,

PD4481181,

PD4481321 and

PD4481361 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

The

PD4481161,

PD4481181,

PD4481321 and

PD4481361 are packaged in 100-pin PLASTIC LQFP with a

1.4 mm package thickness or 165-pin TAPE FBGA for high density and low capacitive loading.

Features

•

Low voltage core supply (A version : V

= 3.3 ± 0.165V, C version : V

= 2.5 ± 0.125V)

•

Synchronous operation

•

100 percent bus utilization

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

All registers triggered off positive clock edge

•

3.3V or 2.5V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 - /BW4 (

PD4481321 and

PD4481361), /BW1 - /BW2 (

PD4481181 and

PD4481181)

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15561EJ1V0DS00 (1st edition)

Date Published June 2001 NS CP(K)

Printed in Japan

2001

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