OptiPHY™-F155 STS-3/STM-1 SONET/
SDH ATM/POS Framer Family
Data Sheet
CX29704 Four STS-3/STM-1 Ports
CX29702 Two STS-3/STM-1 Ports
CX29701 One STS-3/STM-1 Port
500034C
July 2002
Ordering Information
Model Number
CX29704
CX29702
CX29701
Manufacturing Part
Number
CX29704-13
CX29702-13
CX29701-13
Package
27
×
27, 272-Pin PBGA
27
×
27, 272-Pin PBGA
27
×
27, 272-Pin PBGA
Description
4xSTS-3/STM-1
2xSTS-3/STM-1
1xSTS-3/STM-1
Operating Temperature
–40 to 85
°
C
–40 to 85
°
C
–40 to 85
°
C
Revision History
Revision
A
B
C
Level
—
—
—
Date
June 2001
July 2001
July 2002
Description
Formerly Conexant document number
101344A.
Corrected Figure 12.1.
Data sheet now reflects CX2970x family of
devices. Major reorganization throughout.
Added new features that were added to the
CX2970x-13 family, specifically additional APS
support.
© 2001, 2002,
Mindspeed Technologies™, A Conexant Business
All Rights Reserved.
Information in this document is provided in connection with Mindspeed Technologies (“Mindspeed”) products. These materials are provided by
Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or
omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed
makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Mindspeed’s Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever.
THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE
AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR
OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF
THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE
LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST
REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
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The following are trademarks of Conexant Systems, Inc.: Mindspeed Technologies™, the Mindspeed™ logo, and “Build It First”™. Product
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For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at
www.mindspeed.com
which is
incorporated by reference.
500034C
Mindspeed Technologies
™
CX2970x
OptiPHY™-F155 STS-3/STM-1 SONET/SDH ATM/POS Framer
Distinguishing Features
The CX2970x family of integrated circuits implements SONET/SDH processing and ATM/
Packet-Over-SONET(POS)/SDH at 155.52 Mbps. Each component in the family contains both
• Three devices in the STS-3/
STM-1 ATM/POS family based
the PMD and the TC sublayers and provides an UTOPIA Level 2 interface to the ATM layer or a
on port count:
POS Level 2 interface to the link layer. Mindspeed software drivers complete the physical layer
– CX29704 - four ports
solution.
– CX29702 - two ports
Major functional blocks of the devices include: LVPECL line interfaces, clock and data recovery
– CX29701 - one port
(CDR) circuits, transmit clock synthesizer, SONET/SDH framers, 16-bit Utopia/POS level 2
• Software for industry leading
complete solution:
system interface, and control/status interfaces. The control interface includes a simple 16-bit
– CX2970x Telecom
microprocessor interface and a serial SONET/SDH Section/Line DCC byte interface. An alarm
Application Package
and status serial interface (ASSI) provides access to alarm and status information. An industry
(CX2970xTAP)
standard IEEE 1149.1 JTAG interface is provided for board level testing.
– CX28299 Automatic
Functional Block Diagram
Protection Switching
(APS) Software Package
TxD3+/-
RxD3+/-
SD3
PORT 4
TxData[15:0]
TxAdd[4:0]
TxD2+/-
RxD2+/-
SD2
TxD1+/-
RxD1+/-
SD1
PORT 3
TxSOC/P[3:0]
*TxEnb[3:0]
TxClav/PTPAx4
PORT 2
Tx_STPA
TxPrty
TxCLK
Tx_ERR
Tx_EOP
Tx_MOD
RxData[15:0]
RxAdd[4:0]
RxSOC/P[3:0]
*RxEnb[3:0]
RxClav/PRPAx4
TxD0+
TxD0-
Parallel to
Serial
Tx
SONET/
SDH
Framer
Tx
Overhead
Processor
PORT 0
Tx ATM
Cell
Processor
Tx POS
Processor
Rx POS
Processor
Rx ATM
Cell
Processor
FIFO
UTOPIA
Level 2 /
POS-PHY
Interface
FIFO
RxD0+
RxD0-
SD0
RefCLK
Data &
Clock
Recovery
Serial to
Parallel
Rx
SONET/
SDH
Framer
FIFO
Rx_RVAL
RxPrty
RxCLK
Rx_ERR
Rx_EOP
Rx_MOD
Rx
Overhead
Processor
FIFO
Clock
Synthesis
Sec./Line DCC i/f
Microprocessor
Interface
ASSI
JTAG
Interface
TSDCC 1-4
TSDCK 1-4
TLDCC 1-4
TLDCK 1-4
RSDCC 1-4
RSDCK 1-4
RLDCC 1-4
RLDCK 1-4
*READY
*ASSTB
PCAP0
NCAP0
REXT0
REXT1
*DSTB
ASCLK
D[15:0]
*TRST
*INTR
ASDO
TDI
TDO
TCK
CS*
A[8:0]
W/*R
TMS
101344_001
500034C
Mindspeed Technologies
™
iii
-Continued from Front-
The CX2970x LVPECL line interface provides a simple interface to industry standard optical transceiver modules. The integrated
clock and data recovery and transmit synthesis circuits are compliant with Bellcore GR-253 jitter standards. In the transmit
direction the SONET/SDH framers generate all section, line, and path overhead bytes in addition to implementing framing,
scrambling and alarm indication functions. On the receive path, all framing, descrambling, alarm detection, and pointer
processing is performed. A serial interface inserts and extracts the section or line DCC bytes. The CX2970x has complete set of
ATM cell processing functions including: cell encapsulation, HEC calculation, cell delineation, payload scrambling/descrambling
and idle cell insertion/filtering. The POS processing features of the CX2970x include: HDLC framing, scrambling/descrambling,
interframe fills, FIFO management and stuffing/destuffing operations. For both ATM and POS applications a combined Utopia
Level 2/POS Level 2 16-bit interface operates at 50 MHz to support a maximum throughput of 800 Mb/s.
Software for the CX2970x is available on the Mindspeed web site and includes the CX2970x Telecom Application Package (TAP)
and the CX28299 Automatic Protection Switching (APS) software. The CX2970x TAP software is compliant with telecom
standards and includes device initialization code, configuration and diagnostic parameters, and support for failure and
performance monitoring according to applicable telecom standards. A debug monitor can optionally be compiled to assist in
initial hardware debugging. The CX28299 APS software supports linear 1+1, linear 1:n, and Unidirectional Path Switched Rings
(UPSR). The CX28299 APS software utilizes the bridging and switching features of the CX2970x family to implement a complete
physical layer APS solution that is transparent to the ATM/Link layer devices.
An evaluation module (EVM) is available from Mindspeed that demonstrates the features of the CX2970x family of devices. The
CX2904-CN8237 ATM/POS EVM includes the Mindspeed CX29704 ATM/POS PHY and the Mindspeed CN8237 ATM SAR
devices along with four optical transceiver modules in a standard PCI form factor card that can be used with most PC
motherboards. The POS system interface is accessible through two 50-pin connectors. Customers can accelerate their time-to-
market by using the evaluation module as a way to become familiar with the device. For complete EVM details including
schematics, board layout, and bill of material information, see the Mindspeed web site.
Data Sheet
Mindspeed Technologies
™
500034C
-Continued Distinguishing Features-
•
•
APS bridging and switching functions
built in
Receive clock and data recovery and
transmit clock synthesis compliant with
Telcordia GR-253 jitter standards
Full processing of SONET/SDH section,
line, and path overhead bytes
UTOPIA Level 2 and Packet Over SONET
(POS) Level 2 system interface
ATM cell and POS packet processing
Clock and data activity detectors and
level sensors for UTOPIA/POS system
interface debugging
ATM Cell and POS Packet Processing
•
•
4-cell FIFO buffers for both receive and
transmit directions in ATM mode
Cell encapsulation/delineation, payload
scrambling/descrambling, and idle cell
insertion/filtering
16-bit UTOPIA Level 2 Interface
according to the ATM Forum UTOPIA
Level 2 Specification
ATM cell UDF2 byte overwrite via control
register for each port
256-byte FIFO buffers for both receive
and transmit directions in POS mode
Packet HDLC scrambling/descrambling,
frame generation/delineation, byte
stuffing/destuffing, and FCS generation/
verification
16-bit POS Level 2 interface to a link
layer device
POS interface supports Normal and Hot
selection
Utopia/POS Dual-port mapping in
conjunction with SONET/SDH APS
mechanism facilitates quick recovery at
Failure Protection State
Electro-mechanical
•
•
•
•
•
272-pin PBGA, 27
×
27 mm
Industrial temperature range (
–
40 °C to
+85 °C)
3.3 V, 0.35 µm CMOS technology with
5 V input tolerance
TTL and CMOS outputs
Typical power consumption:
CX29704: 2.13W; CX29702: 1.95W;
CX29701: 1.89W
All devices in the CX2970x family
(CX29704/2/1) are pin compatible
•
•
•
•
•
•
•
•
•
Standards Compliance
•
•
Telcordia GR-253, ITU-G.707 and ANSI
T1.105
ATM Forum User Network Interface V3.1
Specification and physical layer
specification for B-ISDN according to
ITU-T recommendation I.432
Point-to-Point Protocol (PPP) over
SONET/SDH specification (RFC 2615 of
the IETF)
Line Interface
•
•
•
On-chip clock and data recovery (CDR)
and transmit clock synthesis
Serializer and de-serializer circuits
Industry standard serial LVPECL
interface to external optical transceivers
•
•
•
•
SONET/SDH Framer Functions
•
•
•
•
•
Monitor A1/A2 framing and recover byte
alignment from incoming serial data
Capture and insertion of all SONET/SDH
overhead bytes
Frame scrambling and descrambling
Byte Interleaved Parity (BIP) processing
Receive Pointer Processing to identify
payload location within the STS-3/STM-
1 frame
Line and Path Alarm indication signal
(AIS) detection and generation
Remote Defect and Remote Error
indication (RDI/REI) processing
Data Communication byte extraction and
insertion for line (D1-D3) and path (D4-
D12) bytes via serial interfaces
Performance and failure monitoring
(PM/FM) via status and error counters
Applications
•
•
•
•
•
Switches
Routers
DSLAMs
Cellular base station infrastructure
Add/Drop Muxes (ADMs)
Control and Status
•
Asynchronous SRAM-like
microprocessor interface with 16-bit
data bus for configuration, control, and
status indications
Open drain interrupt output
Alarm and Status Serial Interface (ASSI)
Transmit and Receive serial interfaces
for Section and Line DCC octets
•
•
•
•
•
•
Test and Debug
•
•
•
•
Line, SONET, and ATM/POS loopbacks
for system debug
SONET/SDH, cell, and packet error
insertion capability
Utopia/POS-PHY interface activity
monitoring for diagnostics and debug
Boundary Scan (JTAG) support in
accordance with IEEE 1149.1 for test
board purposes
•
Automatic Protection Switching (APS)
Support
•
Supports unidirectional and
bi-directional linear 1+1 and linear 1:n
APS architectures
Supports
Unidirectional Path
•
Switched Ring (UPSR) APS
architectures
•
•
Full control and processing of Line K1/
K2 octets
Bit Error Rate (BER) calculations
performed in hardware for SD/SF alarm
triggering
Utopia/POS port bridging and switching
functionality allows APS solution which
is transparent to ATM/Link layer devices
•
500034C
Mindspeed Technologies
™
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