CY7C133
CY7C143
2K x 16 Dual-Port Static RAM
Features
•
True dual-ported memory cells which allow
simultaneous reads of the same memory location
•
2K x 16 organization
•
0.65-micron CMOS for optimum speed/power
•
High-speed access: 25/35/55 ns
•
Low operating power: I
CC
= 150 mA (typ.)
• Fully asynchronous operation
•
Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
•
BUSY output flag on CY7C133; BUSY input flag on
CY7C143
•
Available in 68-pin PLCC
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/W
UB
, R/W
LB
), and Output Enable (OE).
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
Logic Block Diagram
CE
L
R/W
LUB
CE
R
R/W
RUB
R/W
LLB
OE
L
R/W
RLB
OE
R
I/O
8L
– I/O
15L
I/O
0L
– I/O
7L
BUSY
L[1]
A
10L
A
0L
ADDRESS
DECODER
I/O
CONTROL
I/O
CONTROL
I/O
8R
– I/O
15R
I/O
0R
– I/O
7R
BUSY
R
[ ]
1
MEMORY
ARRAY
ADDRESS
DECODER
A
10R
A
0R
CE
L
OE
L
R/W
LUB
R/W
LLB
ARBITRA
TION
LOGIC
(CY7C133 ONLY)
CE
R
OE
R
R/W
RUB
R/W
RLB
Note:
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
Cypress Semiconductor Corporation
Document #: 38-06036 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised June 22, 2004
CY7C133
CY7C143
Pin Configuration
68-Pin LCC/PLCC
Top View
I/O 3L
I/O 2L
I/O 1L
I/O 0L
V CC
R/WLUB
R/WLLB
OEL
I/O 6L
I/O 5L
I/O 8L
I/O 7L
I/O 4L
A10L
A9L
A8L
A7L
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
I/O8R
I/O9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
R/W
RUB
R/W
RLB
OE R
A
10R
A9R
A
8R
A7R
A6R
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
BUSY
L
CE
L
CE
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
9 8 7 6
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
5 4 3 2 1 68 67 66 65 64 63 62 61
7C133
7C143
Selection Guide
7C133-25
7C143-25
Maximum Access Time
Typical Operating Current I
CC
Typical Standby Current for I
SB1
25
170
40
7C133-35
7C143-35
35
160
30
7C133-55
7C143-55
55
150
20
Unit
ns
mA
mA
Document #: 38-06036 Rev. *B
Page 2 of 13
CY7C133
CY7C143
Architecture
The CY7C133 (master) and CY7C143 (slave) consist of an
array of 2K words of 16 bits each of dual-port RAM cells, I/O
and address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. The CY7C133 and
CY7C143 have an automatic power-down feature controlled by CE.
Each port is provided with its own output enable control (OE), which
allows data to be read from the device.
One master and as many slaves as necessary may be
connected in parallel to expand the data bus width in 16 bit
increments. The BUSY output of the master is connected to the
BUSY input of the slave. Writing to slave devices must be delayed
until after the BUSY input has settled (t
BLC
or t
BLA
). Otherwise, the
slave chip may begin a write cycle during a contention
situation.
Flow-Through Operation
The CY7C133/143 has a flow-through architecture that facili-
tates repeating (actually extending) an operation when a
BUSY is received by a losing port. The BUSY signal should be
interpreted as a NOT READY. If a BUSY to a port is active, the
port should wait for BUSY to go inactive, and then extend the
operation it was performing for another cycle. The timing
diagram titled, “Timing waveform with port to port delay” illus-
trates the case where the right port is writing to an address and
the left port reads the same address. The data that the right
port has just written flows through to the left, and is valid either
t
DDD
after the falling edge of the write strobe of the left port, or
t
DDD
after the data being written becomes stable.
Data Retention Mode
The CY7C133/143 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (4.5V).
Timing
Data Retention Mode
V
CC
4.5V
V
CC
>
2.0V
4.5V
t
RC
V
IH
Functional Description
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1 waveform) or
the CE pin (see Write Cycle No. 2 waveform). Two R/W pins (R/W
UB
and R/W
LB
) are used to separate the upper and lower bytes of IO.
Required inputs for non-contention operations are summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flow-through
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after OE is
asserted.
Busy
The CY7C133 (master) provides on-chip arbitration to resolve
simultaneous memory location access (contention).
Table 2
shows a summery of conditions where BUSY is asserted. If both
ports’ CEs are asserted and an address match occurs within t
PS
of
each other, the busy logic will determine which port has access. If t
PS
is violated, one port will definitely gain permission to the location, but
which one is not predictable. BUSY will be asserted t
BLA
after an
address match or t
BLC
after CE is taken LOW. The results of all eight
arbitration possibilities are summarized in
Table 3.
BUSY is an open
drain output and requires a pull-up resistor.
CE
V
CC
to V
CC
– 0.2V
Parameter
ICC
DR1
Note:
2. CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
Test Conditions
[2]
@ VCC
DR
= 2V
Max.
1.5
Unit
mA
Document #: 38-06036 Rev. *B
Page 3 of 13
CY7C133
CY7C143
Table 1. Non-Contending Read/Write Control
Control
R/W
LB
X
L
L
H
L
H
H
H
R/W
UB
X
L
H
L
H
L
H
H
CE
H
L
L
L
L
L
L
L
OE
X
X
L
L
H
H
L
H
I/O
0
–I/O
8
High Z
Data In
Data In
Data Out
Data In
High Z
Data Out
High Z
I/O
I/O
9
–I/O
17
High Z
Data In
Data Out
Data In
High Z
Data In
Data Out
High Z
Operation
Deselected: Power-Down
Write to Both Bytes
Write Lower Byte, Read Upper Byte
Read Lower Byte, Write Upper Byte
Write to Lower Byte
Write to Upper Byte
Read to Both Bytes
High Impedance Outputs
Table 2. Address BUSY Arbitration
Inputs
CE
L
X
H
X
L
CE
R
X
X
H
L
Address
L
Address
R
No Match
Match
Match
Match
BUSY
L
H
H
H
Note 3
Outputs
BUSY
R
H
H
H
Note 3
Normal
Normal
Normal
Write Inhibit
[4]
Function
32-Bit Master/Slave Dual-Port Memory Systems
R/W
LEFT
CY7C133
BUSY
BUSY
RIGHT
R/W
5V
R/W
CY7C143
BUSY
5V
R/W
BUSY
Table 3. Arbitration Results
Port
Case
1
2
3
4
5
6
7
8
Left
Read
Read
Read
Read
Write
Write
Write
Write
Right
Read
Read
Write
Write
Read
Read
Write
Write
Winning Port
L
R
L
R
L
R
L
R
Both ports read
Both ports read
L port reads OK R port write inhibited
R port writes OK L port data may be invalid
L port writes OK R port data may be invalid
R port reads OK L port write inhibited
L port writes OK R port write inhibited
R port writes OK L port write inhibited
Result
Notes:
3. The loser of the port arbitration will receive BUSY = “L” (BUSY
L
or BUSY
R
= “L”). BUSY
L
and BUSY
R
cannot both be LOW simultaneously.
4. Writes are inhibited to the left port when BUSY
L
is LOW. Writes are inhibited to the right port when BUSY
R
is LOW.
Document #: 38-06036 Rev. *B
Page 4 of 13
CY7C133
CY7C143
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
.....................................................−0.5V
to +7.0V
DC Input Voltage
................................................. −3.5V
to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
V
CC
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
7C133-25
7C143-25
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
I
SB3
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Output Short Circuit
Current
[6, 7]
V
CC
Operating Supply Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
CE = V
IL
,
Outputs Open, f = f
MAX[8]
Com’l
Ind.
Com’l
Ind.
Com’l
Ind.
Com’l
Ind.
170
170
40
40
100
100
3
3
90
90
−5
−5
I
OL
= 4.0 mA
I
OL
= 16.0 mA
[5]
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
Min.
2.4
Typ.
Max.
0.4
0.5
Unit
V
V
V
2.2
0.8
+5
+5
−200
250
290
60
75
140
160
15
15
120
140
V
µA
µA
mA
mA
mA
mA
mA
Standby Current Both Ports, TTL CE
L
and CE
R
> V
IH
, f = f
MAX[8]
Inputs
Standby Current One Port, TTL
Inputs
Standby Current Both Ports,
CMOS Inputs
Standby Current One Port,
CMOS Inputs
CE
L
or CE
R
> V
IH
, Active Port
Outputs Open, f = f
MAX[8]
Both Ports CE
L
and CE
R
> V
CC
–
0.2V, V
IN
> V
CC
– 0.2V or V
IN
<
0.2V, f = 0
I
SB4
One Port CE
L
or CE
R
> V
CC
– 0.2V, Com’l
V
IN
> V
CC
– 0.2V or
Ind.
V
IN
< 0.2V, Active Port Outputs Open,
f = f
MAX[8]
mA
Electrical Characteristics
Over the Operating Range (continued)
7C133-35
7C143-35
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current GND < V
I
< V
CC
−5
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
I
OL
= 4.0 mA
I
OL
= 16.0 mA
[5]
2.2
0.8
+5
−5
Min.
2.4
0.4
0.5
2.2
0.8
+5
Typ.
Max.
Min.
2.4
0.4
0.5
V
V
µA
7C133-55
7C143-55
Typ.
Max.
Unit
V
V
Notes:
5. BUSY pin only.
6. Duration of the short circuit should not exceed 30 seconds.
7. Tested initially and after any design or process changes that may affect these parameters.
8. At f=f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t
RC
and using AC Test Waveforms input levels of GND to 3V.
Document #: 38-06036 Rev. *B
Page 5 of 13
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