CY7C133-55JCT datasheet, PDF - EEWORLD Datasheet

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CY7C133-55JCT: DescriptionDual-Port SRAM, 2KX16, 55ns, CMOS, PQCC68, PLASTIC, LCC-68; Categorystorage storage; File Size512KB，13 Pages; ManufacturerCypress Semiconductor

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CY7C133-55JCT Overview

Dual-Port SRAM, 2KX16, 55ns, CMOS, PQCC68, PLASTIC, LCC-68

CY7C133-55JCT Parametric

Parameter Name	Attribute value
Maker	Cypress Semiconductor
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	68
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	55 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	S-PQCC-J68
length	24.2316 mm
memory density	32768 bit
Memory IC Type	DUAL-PORT SRAM
memory width	16
Number of functions	1
Number of ports	2
Number of terminals	68
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2KX16
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	5.08 mm
Minimum standby current	2 V
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	24.2316 mm

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CY7C133

CY7C143

2K x 16 Dual-Port Static RAM

Features

•

True dual-ported memory cells which allow

simultaneous reads of the same memory location

•

2K x 16 organization

•

0.65-micron CMOS for optimum speed/power

•

High-speed access: 25/35/55 ns

•

Low operating power: I

= 150 mA (typ.)

• Fully asynchronous operation

•

Master CY7C133 expands data bus width to 32 bits or

more using slave CY7C143

•

BUSY output flag on CY7C133; BUSY input flag on

CY7C143

•

Available in 68-pin PLCC

Functional Description

The CY7C133 and CY7C143 are high-speed CMOS 2K by 16

dual-port static RAMs. Two ports are provided permitting

independent access to any location in memory. The CY7C133

can be utilized as either a stand-alone 16-bit dual-port static

RAM or as a master dual-port RAM in conjunction with the

CY7C143 slave dual-port device in systems requiring 32-bit or

greater word widths. It is the solution to applications requiring

shared or buffered data, such as cache memory for DSP,

bit-slice, or multiprocessor designs.

Each port has independent control pins; Chip Enable (CE),

Write Enable (R/W

, R/W

), and Output Enable (OE).

BUSY signals that the port is trying to access the same

location currently being accessed by the other port. An

automatic power-down feature is controlled independently on

each port by the Chip Enable (CE) pin.

The CY7C133 and CY7C143 are available in 68-pin PLCC.

Logic Block Diagram

R/W

LUB

R/W

RUB

R/W

LLB

R/W

RLB

I/O

– I/O

15L

I/O

– I/O

BUSY

L[1]

10L

ADDRESS

DECODER

I/O

CONTROL

I/O

CONTROL

I/O

– I/O

15R

I/O

– I/O

BUSY

[ ]

MEMORY

ARRAY

ADDRESS

DECODER

10R

R/W

LUB

R/W

LLB

ARBITRA

TION

LOGIC

(CY7C133 ONLY)

R/W

RUB

R/W

RLB

Note:

1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.

Cypress Semiconductor Corporation

Document #: 38-06036 Rev. *B

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised June 22, 2004

CY7C133-55JCT Related Products

	CY7C133-55JCT	CY7C133-35JCT	CY7C133-25JCT	CY7C133-35JIT	CY7C133-25JIT
Description	Dual-Port SRAM, 2KX16, 55ns, CMOS, PQCC68, PLASTIC, LCC-68	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68	Dual-Port SRAM, 2KX16, 25ns, CMOS, PQCC68, PLASTIC, LCC-68	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68	Dual-Port SRAM, 2KX16, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
Parts packaging code	LCC	LCC	LCC	LCC	LCC
package instruction	QCCJ,	QCCJ,	QCCJ,	QCCJ,	QCCJ,
Contacts	68	68	68	68	68
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Maker	Cypress Semiconductor	-	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Maximum access time	55 ns	35 ns	25 ns	35 ns	-
Other features	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	-
JESD-30 code	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68	-
length	24.2316 mm	24.2316 mm	24.2316 mm	24.2316 mm	-
memory density	32768 bit	32768 bit	32768 bit	32768 bit	-
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	-
memory width	16	16	16	16	-
Number of functions	1	1	1	1	-
Number of ports	2	2	2	2	-
Number of terminals	68	68	68	68	-
word count	2048 words	2048 words	2048 words	2048 words	-
character code	2000	2000	2000	2000	-
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-
Maximum operating temperature	70 °C	70 °C	70 °C	85 °C	-
organize	2KX16	2KX16	2KX16	2KX16	-
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	-
Exportable	YES	YES	YES	YES	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	QCCJ	QCCJ	QCCJ	QCCJ	-
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	-
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	-
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	5.08 mm	5.08 mm	5.08 mm	5.08 mm	-
Minimum standby current	2 V	2 V	2 V	2 V	-
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	-
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	-
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	-
surface mount	YES	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	CMOS	-
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	-
Terminal form	J BEND	J BEND	J BEND	J BEND	-
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	-
Terminal location	QUAD	QUAD	QUAD	QUAD	-
width	24.2316 mm	24.2316 mm	24.2316 mm	24.2316 mm	-

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