K4T51163QE
DDR2 SDRAM
512Mb E-die DDR2 SDRAM Specification
Industrial Temp.
84FBGA with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.01 November 2007
K4T51163QE
DDR2 SDRAM
DDR2-667 5-5-5
K4T51163QE-ZIE6
K4T51163QE-ZPE6
K4T51163QE-ZDE6
DDR2-533 4-4-4
K4T51163QE-ZID5
K4T51163QE-ZPD5
DDR2-400 3-3-3
K4T51163QE-ZICC
K4T51163QE-ZPCC
84 FBGA
Package
Ordering Information
Org.
32Mx16
DDR2-800 6-6-6
K4T51163QE-ZIF7
K4T51163QE-ZPF7
Note : 1. Speed bin is in order of CL-tRCD-tRP
2. RoHS Compliant
3. “I” of Part Number(12th digit) stand for Industrial Temp./Normal Power products
4. “P” of Part Number(12th digit) stand for Industrial Temp./Low Power products
5. “D” of Part Number(12th digit) stand for Industrial Temp./Super Low Power products
Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-800
6-6-6
6
15
15
60
DDR2-667
5-5-5
5
15
15
60
DDR2-533
4-4-4
4
15
15
60
DDR2-400
3-3-3
3
15
15
55
Units
tCK
ns
ns
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/
pin, 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/
sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
-PASR(Partial Array Self Refresh)
-50ohm ODT
-Support Industrial Temp.(Case Temp. -40 to 95°C)
• Average Refresh Period 7.8us at -40°C < T
CASE
< 95
°C
• All of Lead-free products are compliant for RoHS
The 512Mb DDR2 SDRAM is organized as a 8Mbit x 16 I/Os x 4
banks device. This synchronous device achieves high speed dou-
ble-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 device is available in 84ball FBGAs(x16).
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
Rev. 1.01 November 2007
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