F75223
F75223
BIOS Guard
Release Date: Oct 2011
Version: V0.15P
Oct.
, 2011
V0.15P
F75223
F75223 Datasheet Revision History
Version
V0.10P
V0.11P
V0.12P
V0.13P
V0.14P
V0.15P
V0.16P
Date
2011/8
2011/8
2011/8
2011/09
2011/10
2011/11
2012/01
Page
-
26
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--
--
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Revision History
Preliminary Version
Update Application Circuit
Typo correction
Update Package Information / Register Descirption.
Update Package Information / Register Descirption.
Update Register Description
Add New Function Description
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury.
Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
Table of Content
Oct.
, 2011
V0.15P
F75223
1. General Description .............................................................................................................. 4
2. Feature List ........................................................................................................................... 4
3. Key Specification................................................................................................................... 5
4. Block Diagram....................................................................................................................... 5
5. Pin Configuration .................................................................................................................. 6
6. Pin Description ...................................................................................................................... 7
Power Pin ........................................................................................................................... 7
SMBUS Interface ............................................................................................................... 7
Host SPI Interface .............................................................................................................. 7
Slave SPI Interface............................................................................................................. 7
System Signal Interface ..................................................................................................... 8
Flash status ........................................................................................................................ 8
7. Function Description ............................................................................................................. 8
7.1 Power On Trapping ..................................................................................................... 8
7.2 SPI .............................................................................................................................. 8
7.3 System Signal ............................................................................................................. 9
7.4 Flash strap and status ............................................................................................... 10
7.5 WDT .......................................................................................................................... 11
7.6 Auto Refreshing ........................................................................................................ 12
8. Register Description............................................................................................................ 15
9. Electrical Characteristics ..................................................................................................... 21
9.1 Absolute Maximum Ratings ...................................................................................... 21
9.2 DC Characteristics .................................................................................................... 21
9.3 AC Characteristics .................................................................................................... 22
10.Ordering Information .......................................................................................................... 24
11.Top Marking Specification .................................................................................................. 24
12.Package Dimensions ......................................................................................................... 25
13.Application Circuit .............................................................................................................. 26
Oct.
, 2011
V0.15P
F75223
1. General Description
The F75223 is a BIOS Guard which can copy the BIOS code from one SPI flash to another. The
F75223 provides an interface to connect 2 SPI flashes and supports manual/auto mode option. Mode
option can be decided by hardware strapping (by PWROK pin) or register setting.
Two SPI flashes can be assumed to flash A and flash B. For manual mode, the F75223 controls flash
A or B to read or program by the SPI host which means only one flash could be accessed by the SPI host.
For auto mode, the F75223 sequentially controls flash A and B to read or program by the SPI host.
F75223 provides a watch dog timer and PWROK detect function. When system power on, the WDT
function will count down to zero and the PWROK status would be detected in the meantime. Timeout or
the PWROK failure will trigger the reset signal to the system and sequentially change to backup flash for
booting. Also, the F75223 would alternate the flash when PWROK failure occurs.
The F75223 is programmed by SMBUS interface, and only support Byte Read/Write protocol. The
chip is powered by VSB and packaged in 20 QFN Green Spec.
2. Feature List
General Functions
Bi-directional BIOS recovery
Manual copy by button (low pulse, de-bounce 4 seconds)
Strap status when PWROK rising and load to state machine immediately
4 modes of LED status blinking (A, B, burn in from B to A or A to B)
WDT timer (1sec ~ 16sec, default 10sec)
PWROK counter
Power-Down mode
Programmable SPI command, register include
Chip Erase command (0xC7)
Read command (0x03)
Program command (0x02)
Write enable command (0x06)
Write disable command (0x04)
Read status command (0x05)
Enable Write Status command (0x50)
Write Status command (0x01)
Long Wait time register
Package
20-pin QFN Green Package
4
Jan., 2012
V0.16P
F75223
3. Key Specification
Supply Voltage
Maximum Operation Supply Current (VSB)
Idle Current (VSB)
Power Down Mode Current (VSB)
VBAT Current (Operation / Idel / Power Down)
3.0V to 3.6V
5mA
3.5mA
10uA
<1uA
Max.
Max.
Max
4. Block Diagram
ACCESS POINT
I2C interface
WDT
Flash B
HOST
CORE Controler
Flash A
LED Control
Internal 34MHz
Clock
POWER DOWN
Control
F75223N
5
Jan., 2012
V0.16P
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