EDD5108AFBG-6B-E datasheet, PDF

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EDD5108AFBG-6B-E: Description512M bits DDR SDRAM; Categorystorage storage; File Size584KB，52 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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EDD5108AFBG-6B-E Overview

512M bits DDR SDRAM

EDD5108AFBG-6B-E Parametric

Parameter Name	Attribute value
Maker	ELPIDA
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	60
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
JESD-609 code	e1
length	12.5 mm
memory density	536870912 bi
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	60
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	10 mm

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PRELIMINARY DATA SHEET

512M bits DDR SDRAM

EDD5108AFBG (64M words

8 bits)

EDD5116AFBG (32M words

16 bits)

Specifications

•

Density: 512M bits

•

Organization



16M words

8 bits

4 banks (EDD5108AFBG)



8M words

16 bits

4 banks (EDD5116AFBG)

•

Package: 60-ball FBGA



Lead-free (RoHS compliant)

•

Power supply:



DDR400: VDD, VDDQ

2.6V

0.1V



DDR333: VDD, VDDQ

2.5V

0.2V

•

Data rate: 400Mbps/333Mbps (max.)

•

Four internal banks for concurrent operation

•

Interface: SSTL_2

•

Burst lengths (BL): 2, 4, 8

•

Burst type (BT):



Sequential (2, 4, 8)



Interleave (2, 4, 8)

•

/CAS Latency (CL): 2, 2.5, 3

•

Precharge: auto precharge option for each burst

access

•

Driver strength: normal/weak

•

Refresh: auto-refresh, self-refresh

•

Refresh cycles: 8192 cycles/64ms



Average refresh period: 7.8µs

•

Operating ambient temperature range



TA = 0°C to +70°C

Features

•

Double-data-rate architecture; two data transfers per

clock cycle

•

The high-speed data transfer is realized by the 2 bits

prefetch pipelined architecture

•

Bi-directional data strobe (DQS) is transmitted

/received with data for capturing data at the receiver

•

Data inputs, outputs, and DM are synchronized with

DQS

•

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

•

Data mask (DM) for write data

Document No. E0887E20 (Ver. 2.0)

Date Published November 2006 (K) Japan

Printed in Japan

URL: http://www.elpida.com

This product became EOL in April, 2010.

Elpida

Memory, Inc. 2006

EDD5108AFBG, EDD5116AFBG

CONTENTS

Specifications.................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Speed Grade Compatibility............................................................................................................................2

Pin Configurations .........................................................................................................................................3

Electrical Specifications.................................................................................................................................5

Block Diagram .............................................................................................................................................13

Pin Function.................................................................................................................................................14

Command Operation ...................................................................................................................................16

Simplified State Diagram .............................................................................................................................23

Operation of the DDR SDRAM ....................................................................................................................24

Timing Waveforms.......................................................................................................................................43

Package Drawing ........................................................................................................................................49

Recommended Soldering Conditions..........................................................................................................50

Preliminary Data Sheet E0887E20 (Ver. 2.0)

EDD5108AFBG-6B-E Related Products

	EDD5108AFBG-6B-E	EDD5108AFBG	130145-0080	EDD5108AFBG-5C-E	EDD5116AFBG-5B-E	EDD5116AFBG-6B-E
Description	512M bits DDR SDRAM	512M bits DDR SDRAM	Safeway Connector with Locking Blade, 3 Pole/4 Wire, NEMA L16-30, 3 480V	512M bits DDR SDRAM	512M bits DDR SDRAM	512M bits DDR SDRAM
Maker	ELPIDA	-	-	ELPIDA	ELPIDA	ELPIDA
Parts packaging code	BGA	-	-	BGA	BGA	BGA
package instruction	TFBGA,	-	-	TFBGA,	TFBGA,	TFBGA,
Contacts	60	-	-	60	60	60
Reach Compliance Code	unknow	-	-	unknow	unknow	unknow
ECCN code	EAR99	-	-	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	-	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.7 ns	-	-	0.7 ns	0.7 ns	0.7 ns
Other features	AUTO/SELF REFRESH	-	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60	-	-	R-PBGA-B60	R-PBGA-B60	R-PBGA-B60
JESD-609 code	e1	-	-	e1	e1	e1
length	12.5 mm	-	-	12.5 mm	12.5 mm	12.5 mm
memory density	536870912 bi	-	-	536870912 bi	536870912 bi	536870912 bi
Memory IC Type	DDR DRAM	-	-	DDR DRAM	DDR DRAM	DDR DRAM
memory width	8	-	-	8	16	16
Number of functions	1	-	-	1	1	1
Number of ports	1	-	-	1	1	1
Number of terminals	60	-	-	60	60	60
word count	67108864 words	-	-	67108864 words	33554432 words	33554432 words
character code	64000000	-	-	64000000	32000000	32000000
Operating mode	SYNCHRONOUS	-	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	-	-	70 °C	70 °C	70 °C
organize	64MX8	-	-	64MX8	32MX16	32MX16
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	-	-	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	-	-	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified	-	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	-	-	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	-	-	YES	YES	YES
Maximum supply voltage (Vsup)	2.7 V	-	-	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	-	-	2.5 V	2.5 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	-	-	2.6 V	2.6 V	2.5 V
surface mount	YES	-	-	YES	YES	YES
technology	CMOS	-	-	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	-	-	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN SILVER COPPER	-	-	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	-	-	BALL	BALL	BALL
Terminal pitch	0.8 mm	-	-	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	-	-	BOTTOM	BOTTOM	BOTTOM
width	10 mm	-	-	10 mm	10 mm	10 mm

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